Boundary Scan FAQs
What’s onTAP? onTAP Series 4000 is a comprehensive, graphical, boundary scan tool providing users with a full set of development and test capabilities. onTAP is designed and organized in a logical manner, reflecting the natural progression of tasks related to development and test. The notebook tab order of the screens helps to ensure the creation of thorough, accurate test solutions in a user-friendly environment.
How much time will I need to spend learning about onTAP? onTAP requires considerably less time to learn than almost any other full-featured boundary scan product. In most instances, we can have you up and running a standard interconnect test within hours.
What hardware is required to use onTAP?
onTAP’s USB Programming Cable is all you need to run tests and program FLASH memory devices. Later this year, we will provide support for the Xilinx USB Programming Cable and the Altera USB Blaster. Otherwise, an industry-standard, industry-tested parallel port programming cable will run onTAP tests. These cables may be purchased directly from the manufacturer.
What files are required? A BSDL file is required to run any tests. A board netlist is also required for interconnect and cluster tests.
What is a BSDL file? “Boundary Scan Description Language” files are created by the manufacturer of the boundary scan device. BSDL files provide a map of the device and are available from the manufacturer.
Do you have a library of BSDL devices? Since most device manufacturers have the most up-to-date BSDL files readily available for download from their web sites, we do not maintain a library of BSDL files. in addition, manufacturers of proprietary devices may not have BSDL files available for download and will have to be contacted directly to obtain those files.
What other filename extensions can be used? bsd, .bsdl, and .bsm
What is a netlist? A netlist is simply a map of the Printed Circuit Board (PCB). It describes what devices are plugged into the board, the specifics of the device types and how they are connected together. For example, if your board has 10 devices on it, and only four are JTAG devices, boundary scan software will need to know which devices are going to be tested, and which need to be transparent. The netlist provides that detailed information.
How do I Import netlists? onTAP reads over twenty netlist CAD formats (http://www.flynn.com/products/ontap/ontap-cad-netlists.php). If you do not see your netlist format, contact our Tech Support (support@flynn.com) and ask if a translator can be made.
How do I Quickly merge netlists from various sub-assemblies? onTAP can merge two or more netlists, on a connector-to-connector basis, assuming corresponding pin numbers are on a pin-to-pin basis. The merge procedure requires only a few minutes.
How do I Program programmable devices, such as ATMEL or Xilinx FPGAs or CPLDs, either directly through the JTAG chain or indirectly through a third device, like the memory bus of a JTAG compliant micro? onTAP supports IN-SYSTEM CONFIGURATION of programmable devices via SVF files produced from Xilinx ISE and iMPACT software, Altera Quartus, or Lattice development tools. Utilization of onTAP’s Memory cluster Test Option (included in the evaluation version) is required for testing non-JTAG devices. The onTAP USB cable should be used for large FPGA program files.
How does onTAP allow the automatic generation of short/open tests even when non-scan devices lie between scan pins? Automatic , netlist-based, test generation produces tests for opens, bus-wire, stuck-at, pull-up/pull-down, hard shorts, and mid-state shorts faults. Low Ohm resistors, buffers, transceivers, and logic elements between boundary scan pins and between boundary scan and cluster-test-device pins are modified within onTAP and ATPG uses the models and netlist to make intervening circuits effectively transparent.
How do I perform real-time probing/visualization of the state of observable pins/nodes in the netlist? onTAP test programs can be run straight though on the Test screen where pin-level diagnostic messages are produced. In addition, the ProScan display allows breakpoints to be set and test programs can be single-stepped so that conditions on a board can be probed and compared with waveform values.
How do I perform real-time setting/clearing of a pin/node, allowing me to verify external circuits by probing and using the software user interface to set pin states? ProScan is available allowing any pin to be highlighted, along with all pins on its net. BS pins can be wiggled and test values captured and displayed. Also, SAMPLE mode can be toggled on/off so that background application signal activity, such as clocks, can be observed.
Multiple JTAG Chains: Support for multiple JTAG chains is simple and straightforward. One onTAP USB cable is required per chain, and the USB cables can be run from a powered USB hub. Boundary scan pins are handled interactively between the chains, so that pins on one chain can transmit and receive to and from pins on a different JTAG chain.
Bed-of-Nails ATE: A translator is available for GenRad/Teradyne 228X ICT equipment.
Library of Cluster Test Devices: A library of models (link) is available for many memory (SRAM,SDRAM,DDR2 SDRAM) devices as wells as for programming and verifification of many Flash devices (e.g., Spansion, Strataflash). Please contact us to learn more about the available models for use, or ones that can be made for your application.