Updates
Thank you for your continued interest in onTAP Series 4000.
- All onTAP users with active software maintenance and 30-day evaluation licenses may download updates.
- Updates are cumulative – we strongly advise keeping up with the latest builds.
- For a complete listing of all software changes look in the onTAP online HELP section, "onTAP Change History."
- Please fill in the required information below to receive your updated version of onTAP.
Current build 4161. Updated March 4, 2010
| onTAP Build Change Log |
| Build 4161 |
Corrects problem with IDCODE tests resulting from millisecond delay settings in multi-chain tests or when specified on the Settings page.
|
| Build 4160 |
- Includes updates for programming Lattice FPGAs.
- Upgrades differential pair testing. Reads port groupings of differential pair pins in BSDL files and accounts for all positive and negative side pins using BSDL files and netlist.
|
| Build 4158 |
- Adds Play/Record feature for SVF program configuration files. Play/Record converts SVF files to binary, allowing faster programming. Play / Record can be enabled from the Cables menu for specific SVF files.
- Ensures that guard constraints in the Browse Circuit view are updated when a guard condition is changed the Vector view
|
| Build 4157 |
Improves stability in ProScan debugging environment |
| Build 4156 |
Enables manual input of text in the License Request Folder Edit box on the Help About page. |
| Build 4155 |
Statically links Windows DLLs to enable that user’s have the correct DLLs |
| Build 4153 |
Corrects potential false failures in multi-chain applications
|
| Build 4152 |
Ads stability when generating tests for some multi-JTAG chain applications |
| Build 4151 |
- Corrects problem writing failure reports from Mfg test screen when Operator, Serial Number, and Unit Type text strings are entered.
- Adds pin-wiggling capability on Nets screen and ProScan for the Xilinx USB cable
|
| Build 4150 |
Adds support for Xilinx USB Platfrom Cable (Beta). |
| Build 4149 |
Adds SAMPLE/PRELOAD instruction as a default in first cluster test scan prior to EXTEST instruction. |
| Build 4148 |
- Corrects test generation for circuits with shared control cells to ensure that only one driver on a net is active at one time.
- Moves license file, LogicPinMaps and other files within the onTAP folder to the c:\Flynn Systems Corp\onTAP folder, in order to avoid write protected folders within the c:\Program Files folder. The default installation folder is still c:\Program Files\onTAP.
- Adds code in preparation of support for the Xilinx USB Cable II.
|
| Build 4146 |
Improves coverage for handling guards when current limiting is enabled
|
| Build 4145 |
- Corrects problem with current-limiting option.
- Corrects problem writing serial-number-specific files when testing from the Manufacturing Test screen.
|
| Build 4143 |
- Adds netlist translator support for IPL Wirelist netlists
- Includes adjustment for the current limiting option
|
| Build 4142 |
Changes the Scan switch factor on the Settings page to a current limiting switch factor (CLSF). Values greater than one limit the total number of pins that can be active at one time during the opens, stuck-at, and pull resistor tests. |
| Build 4141 |
Improves handling of edits to attributes and pin-map model assignments on the non-Scan page. |
| Build 4140 |
- Adjusts ground bounce switch factor operation for pull-up/down tests.
- Introduces option to add vectors and extend fault coverage in applications where pins share common tri-state control cells. The option is controlled by the “Alternate drive on pins having common control cells” check box on the settings page and the default setting is enabled.
- Ensures that all eligible pins alternate drive on nets having multiple scan pins.
- Corrects problem showing all LogicPinMap models on the non-Scan page.
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Flynn Systems Corporation, 74 Northeastern Blvd., Nashua, NH 03062
Ph: (603) 598-4444 Fax: (603) 598-4111 sales@flynn.com All rights reserved.