The onTAP Boundary Scan / JTAG Test Development System includes all of the necessary JTAG software tools you need to develop and run comprehensive and reliable onTAP tests, delivering robust JTAG solutions. With over 2 dozen CAD netlist readers, a built-in netlist merge tool, and ProScan – the graphical boundary scan test debug environment – the onTAP Development system will speed up your project development time, and keep costs under control. These tools enable you to quickly and easily develop, run, and debug JTAG tests ranging from single JTAG chain applications, to multiple JTAG chain applications with multi-die modules, merged sub-assemblies, and multi-drop configurations. onTAP can accommodate unlimited JTAG circuit size.
Familiar notebook style pages organize and guide the input of essential test information enabling onTAP’s ATPG to build high fault coverage tests with pin-level diagnostics and comprehensive test reports. Then, run tests and access the graphical ProScan debug screen, built-in netlist browser, and test reports whenever you want to review them.
Some Highlights of onTAP Boundary Scan / JTAG Test Development include:
- CAD Netlist Based – Over 2 Dozen CAD Netlist Readers
- Project Assistant Guides You Through Test Development
- Flash Programming
- Memory Cluster Test
- Includes comprehensive library of DTS models for popular SRAM, SDRAM, DDR2, DDR3, NAND, I2C, and other FLASH devices
- Merge netlists
- User defined tests (BIST)
- Support for multi-drop linkers
- Support for differential pair circuits
- BSDL file syntax and semantics checker
- Support for multi-die devices
- Productivity tools include:
- Automatic chain detection
- Netlist merge
- ProScan graphical debug
- Circuit browser
- Flash data file format translators
- Automatic Test Generation
- Netlist browser
- Familiar notebook style
- onTAP-Specific Interconnect Test
- ProScan Enabled!
- Flexible, reusable, reliable tests
onTAP-Specific Boundary Scan / JTAG Tests
Download onTAP Test Data Sheet PDF
Flynn Systems designed onTAP to be a comprehensive test and programming solution. That is why we have developed boundary scan test strategies specific to onTAP over the past 10 years. These test strategies are highly automated, require minimal user intervention, test beyond the basic boundary scan requirements, and deliver the highest possible fault coverage.
onTAP ATPG is Test-to-Print
- Models non-scan devices such as buffers, bus transceivers, logic elements and resistor packs.
- Automatically manages bidirectional data flow through buffers and transceivers.
- Incorporates pin-level diagnostics
- Manages bus traffic
- Tests for Opens/Shorts
- Tests Pull ups/ pull downs
- Manages Capacitive coupling
- Tests Mid-state/resistive shorts
- Manages Bus wire testing
Flexible and Reusable Boundary Scan / JTAG Tests
When you develop a test with onTAP, your test configuration and settings are automatically saved in your project folder. You can always reopen, reuse, rerun, and make changes to your tests as needed. This feature is especially helpful in situations when your netlist changes as you move through prototyping. Simply swap in the new netlist and adjust settings as required.
onTAP makes this task easy by providing a list of netlists in your project. Simply add any prefix string identifiers that you wish to assign to elements in each netlist. Associate connectors and pins where a netlist merge should occur, and click merge.
Incorporating Multiple JTAG Chains
onTAP enables you to find and define each chain in your application during test development. onTAP will automatically try to define the JTAG chain(s) based on the connections defined by the netlist(s). If that is not available, onTAP will discover the chains through auto detection via a cable link between onTAP and the target board. Moreover, users are free to drag-and-drop devices in to user prescribed order.
Automatic JTAG Chain Detection
This feature is helpful when trying to determine device order in the JTAG chain. onTAP will interrogate the JTAG chain, and discover the proper device order of each JTAG chain present. This tool is useful especially when JTAG devices are not directly connected in a netlist.
Non-Scan Devices: Memory Cluster Tests and Flash Programming (ISP)
Cluster test and Flash programming allows non-scan devices such as, DDR2 memory and flash memory, accessible from JTAG scan pins to be tested and programmed. Flynn Systems maintains an extensive library of flexible and reusable Digital Test Syntax (DTS) models and will make models, tailored to your needs, on request.
Flexible and Reusable Cluster Test and Flash Models
All models are developed using the C-like DTS language. Flynn Systems uses this language because of its ease-of-use, flexibility and familiarity. Rather than building individual, unique models for each device type in a family, DTS models enable simple edits to basic family models and to cover a large number of devices. All of these models and their changes are saved in your project folder, and can be re-used from one project to the next on-the-fly because they are not project specific.