onTAP Turnkey Service

Expert Turnkey Boundary Scan Test Development

onTAP Boudnary Scan JTAG Test Solutions Turnkey Projects Image

Proprietary boundary scan test development procedures include:

  • Flynn Systems’ thorough Interconnect Boundary Scan Test
  • Cluster test model development for testing of non-JTAG memory and flash devices
  • Design for Test (DFT) service
  • Expert evaluation of your board test results and one-on-one online assistance with debug.
  • BSDL syntax verification to IEEE 1149.1b Boundary Scan Specification

How it works

Our boundary scan / JTAG test development process takes advantage of your application knowledge and our onTAP JTAG test development expertise to quickly and economically produce the highest quality boundary scan tests.

When you send us your BSDL and CAD netlist files, plus data sheets for non-JTAG memory and FLASH devices you want to test, we will work closely with you via email and telephone to develop your onTAP boundary scan tests. When you are ready to apply the tests to the board, we assist you while you debug your test, and revise it as necessary to deal with unanticipated board-level and device interactions.

From our experience in developing hundreds of successful boundary scan tests with customers all over the world, we have found this methodology produces the most consistent, successful test results.

Overview of the Test Development Procedure

Step 1. Send us your board netlist, BSDLs, and datasheets

You send us your board netlist, BSDLs, and datasheets for any non-JTAG devices you want to include as a cluster test. Cluster testing non-JTAG devices can significantly boost your overall fault coverage.

Step 2. We generate the test program and the cluster test device models for devices on your board.

This step usually requires some back-and-forth with you to set jumpers and guards to deal with the various interactions between devices on your board.

Step 3. You apply the tests to the board at your facility and let us assist in your test and board debugging.

We can show you how to use onTAP’s diagnostic tools to get visibility into the state of each boundary cell at each scan vector, and single-step through the test. We can assist you in interpreting the diagnostics and edit/regenerate the tests as required.

PCBs can also be sent to Flynn Systems for complete turnkey service or to expedite test development and debug.

Pricing and Lead Time

Pricing for this service is dependent upon the complexity of your board.  We also offer leasing options for onTAP Manufacturing Test licenses.

For a pricing estimate, please send us:

Board netlist

BSDL files for all boundary scan devices on your board.

Datasheets for any non-JTAG devices that you wish to cluster test.

BOM

Schematic

Test development lead time ranges from two days to two weeks depending upon the complexity of the board and the number of cluster test models required. If you require us to sign an NDA, please contact sales@flynn.com to expedite test development quotes.

Printable PDF Describing onTAP Turnkey JTAG Project Solutions PDF Describing onTAP Turnkey JTAG Project Solutions