Flynn Systems » onTAP JTAG Blog

onTAP Supports IEEE 1149.6!

admin — Fri, 14 May 2010 20:26:45 +0000

As we have promised our users, Flynn Systems continues to develop and add new features to onTAP Boundary Scan Software. These new features vastly improve onTAP’s capability, enabling onTAP users to do more with less. We had been developing support for IEEE 1149.6 for several months, and at the end of April, we were able to fully implement the IEEE 1149.6 standard into the current version of onTAP. It has been rigorously field tested, and we are proud to release it to our user community. Please download the newest version of onTAP, and feel free to begin developing truly complete, robust JTAG tests for your projects with IEEE 1149.6 capability.

onTAP Boundary Scan Software Now Supports IEEE 1149.6

NASHUA, NH May 14, 2010 – Flynn Systems Corp is proud to announce the latest version of onTAP is IEEE 1149.6 compliant. The implementation of IEEE 1149.6 greatly enhances onTAP’s scope and capability, while delivering more JTAG test coverage and power to current and interested onTAP users.

According to Ryan Flynn, onTAP Marketing Manager, “As Xilinx and Altera begin to implement IEEE 1149.6 protocols in their latest designs, including the Virtex 6 and Aria GX devices (respectively), it was increasingly important for us to enable onTAP users with every bit of capability so they could harness the full test potential of these new devices and implement them into their designs. onTAP’s IEEE 1149.6 implementation has been field tested in very intense and rigorous applications with Intel. Intel’s success has been a heck of proving ground for onTAP.”

As implementation of IEEE 1149.1 and 1149.X Boundary Scan testing becomes more widespread, greater flexibility, faster speeds, and smoother operation are needed. Flynn Systems’ commitment to its Customers has always been to keep onTAP a live software by continuing to support, develop, and enhance onTAP tools that capitalize on JTAG test capability. The 1149.6 implementation is another demonstration of Flynn’s commitment to its user base.

onTAP’s new update expands users’ test capabilities, flexibility, and further enhances test fault coverage in a number of ways. Most apparent is the productivity gain achieved by testing to both IEEE 1149.1 and IEEE 1149.6 standards. The IEEE 1149.6 feature enables users to test AC Coupled circuits and differential pairs to the industry standard protocol. Adding these two elements to a test not only increases test fault coverage, but also creates a more robust and reliable test by incorporating additional aspects of the board in the test.

Flynn Systems continues its pursuit of delivering cost-effective, complete, robust JTAG test and programming software packages with attentive and dedicated technical support to its current users and anyone interested in a feature-rich, high-value complete JTAG solution at a reasonable price.

About Flynn Systems:

Flynn Systems began delivering Automatic Test Generation Solutions to the ATE market as FS-ATG in 1986. In late 1999, they transitioned to the boundary scan market with onTAP and have provided test, debug, and programming solutions for the boundary scan test standard (JTAG IEEE 1149.1) for over ten years. Their onTAP software package is designed for completely automated boundary scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-boundary scan devices interacting with the scan enabled devices. onTAP’s functionality also includes the capability to program FLASH devices using only the onTAP USB Test and Programming Cable (HighSpeed included). Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. Its satisfied customers include Intel, Qualcom, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona. Flynn Systems’ onTAP provides boundary scan services for university research, avionics, defense systems, consumer goods, and medical electronics. It is based in New Hampshire with distributors and partners in Europe and Asia.

Those interested are invited to download a free 30 day evaluation software package with full technical support available at www.flynn.com.

Groundhog Day Sale

admin — Tue, 02 Feb 2010 21:30:37 +0000

EVERYTHING YOU NEED

Nashua, NH by-way-of Gobbler’s Nob, Punxsutawney, Pennsylvania – Well, it’s official! The groundhog poked out and saw its shadow. Settle in for six more weeks of winter. The upside is, you have six more weeks to not worry about nice sunny days and walks in the park with sunshine on your face. That means more winter time to dedicate to developing and debugging your projects so when spring does finally arrive, you’re ready to take full advantage of the nice spring weather.

We know you’re busy, but bargains are always welcome. Flynn Systems is announcing its Groundhog Day Special.

Even though we all got the bad news that winter is continuing for six more weeks, we want to give you some good news about boundary scan test tools. When you purchase any onTAP Boundary Scan Software license, we are giving you the option to add another license to your package for FREE*. That’s right, FREE. Buy a development seat for the lab, or an MTO for manufacturing, and get another one for a co-worker. You have your choice of an MTO or DLL.

Act fast, this offer only lasts until the first official day of spring – March 20, 2010

We look forward to hearing from you. Please feel free to contact us to discuss your boundary scan application.

THE SMALL PRINT:

*Free onTAP software offer applies to all quotes generated between Feb. 2 2010 and March 20, 2010 and is limited to one free license per quote. Offer is also limited to either an MTO or DLL. Offer expires on March 20, 2010.

Happy New Year – Welcome 2010

admin — Mon, 18 Jan 2010 17:40:17 +0000

We hope everyone is off to a strong and promising 2010. By all signs, it appears that this year will deliver new innovations and products to the electronics market. We certainly are excited to hear about our customers new projects and are looking forward to sharing our new developments with you through out the course of this exciting new year.

Keep an eye for some major upgrades to the software that are sure to greatly increase test capability, usability, and productivity.

Here’s to a successful and prosperous 2010!

Properly Managing Common Tri-State Control Cells Boosts Fault Coverage

admin — Wed, 16 Dec 2009 20:16:00 +0000

As the boundary scan community continues looking for new ways to improve test procedures and achieve higher and higher fault coverage, we expect the test tools to compensate for shortcomings in silicon devices or board design. We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.

Common tri-state control cells are groups of pins on a common net. Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.

Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below.

In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.

The yellow 0 and 1 characters show drive, or boundary register update, values at each test vector, and the green L and H values show expected boundary register capture values on the vectors following an update.

This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.

This image shows how the test was revised to account for the tri-state pins on the common control cell. The result is a boost in fault coverage, with the added benefit of making the test more accurate.

As explained in the text box in this screen shot, onTAP accounts for the shared cells and adds additional test vectors to ensure pins do not drive simultaneously, allowing for more comprehensive tests that deliver higher, and most importantly, more accurate, test fault coverage.

Accepting New Turnkey JTAG Projects

admin — Tue, 17 Nov 2009 20:58:35 +0000

Flynn Systems wants to let our users know that we are accepting new JTAG / Boundary Scan projects for Q1-2/10

While our standard Technical Support provides assistance with test and development issues, our boundary scan test development services go beyond onTAP technical support services by taking the boundary scan / JTAG test development and debugging off your plate, allowing you to focus your undivided attention on your core business issues as you move through development and prototyping into manufacturing.

Our Boundary Scan Test Development Service is very popular with both existing and new customers. In fact, 4 out of 5 customers who have used onTAP boundary scan test development services once, immediately recognize the cost and time savings, and return within 4 months with another project. By turning over your JTAG / Boundary Scan test development to Flynn Systems, you are able focus on other aspects of your project without being distracted by developing and debugging boundary scan tests.

We ensure that your boundary scan tests are maximized for the highest possible fault coverage, are completely debugged, and are ready for the manufacturing floor, so the end user only has to “press a button.”

We support our tests and we will support you and/or your contract manufacturer by answering questions and bringing all parties involved up-to-speed with boundary scan test and onTAP procedures and reports.

Our test development features:

JTAG TAP infrastructure tests.
Interconnect tests including detection of opens, shorts, stuck-at, bus-wire, pull-up/down related faults.
Memory tests
Cluster tests of non-JTAG components
Flash programming
In-system programming configuration
Pin-level diagnostics
On-going support

All of our tests are comprehensive, accurate, supported and reliable.

Call us today to get started.

Click here to learn more about onTAP Turnkey Service

JTAG.TECT Delivers onTAP to Russian Customers

admin — Mon, 09 Nov 2009 22:13:05 +0000

Flynn Systems – StarTest Technology Partnership Press Release

Flynn Systems and StarTest, along with their subsidiary JTAG.TECT (www.jtag-test.ru), have established a strategic relationship making JTAG.TECT the authorized Flynn Systems’ onTAP Boundary Scan Solutions dealer in Russia and countries of the former USSR. JTAG.TECT bundles onTAP Boundary Scan Solutions with their JTAG test solutions and services and provides complete JTAG tutorial and customer consulting, DFT and JTAG test program development support for onTAP. Flynn Systems has also integrated StarTest’s JTAG hardware and software environment with the JTAG test and programming tools of the onTAP Boundary Scan Series 4000.

Current and potential customers of onTAP Boundary Scan Solutions, and onTAP Series 4000 are able to use some of StarTest’s hardware and software solutions (DIMM/SODIMM External Modules, TAP Distributor and Bridge-For-Testability hardware tools, Operator Fault Spotlight software tool), as built-in features of the onTAP Boundary Scan Solution, usable throughout the users’ product lifecycle, including volume manufacturing and in-the-field troubleshooting and repair.

StarTest Ltd. (www.start-test.com) is a leading developer and supplier of JTAG test solutions in Israel across all hardware levels, including device, board, and system. StarTest is a team of test experts and engineers with more than 70 years of combined worldwide experience. StarTestserves as a JTAG and In-System Test (ICT) support supplier for:

Design-For-Testability (DFT) analysis and checking the DFT compliance of customer’s design before board layout and on all stages of the product lifecycle
JTAG (Boundary Scan) test program development, including on-board programming of CPLD, FPGA, flash, I²C, with different tools and platforms
ICT test program development for the Teradyne Z18xx testers with full test process support on the customer production facility

Flynn Systems Corp.(www.flynn.com) has provided test, debug, and programming solutions for the Boundary Scan test standard (JTAG IEEE 1149.1) for over ten years. Their onTAP software package delivers completely automated Boundary Scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-Boundary Scan devices interacting with the scan enabled devices. onTAP’s functionality also includes the capability to program flash devices using only the onTAP USB Test and Programming Cable. Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. Its satisfied customers include Intel, Qualcomm, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona. Flynn Systems’ onTAP provides Boundary Scan services for university research, avionics, defense systems, consumer goods, and medical electronics. It is based in New Hampshire with distributors and partners in Europe and in the Middle East.

onTAP BIST (Built In Self Test)

admin — Wed, 04 Nov 2009 16:47:13 +0000

Tests may be defined in script files which may then be translated into executable Serial Vector Format (SVF) files. The general approach is to place all of the required BSDL files into a folder and then to relate the BSDL files to circuit locations in declarations at the beginning of the script file. Once BIT_STRINGS are defined, instruction register scans may be created by simply declaring the instruction names to be used. And data scans can be created by concatenating BIT_STRINGS. String variables may be assigned values and then multiple variables may be concatenated. In addition literal string assignments may be used directly or mixed with variables.

Values are always expressed as binary strings, BIT_STRINGS. If zero and one values are present in a TDO string, the corresponding MASK bits will be set to one. If ‘X’ characters are present in a TDO string, the corresponding mask bits are set to zero.

The following example shows a very literal application of an IDCODE test to a three device chain. Comments, beginning with the ! character, explain the purpose of each statement and are consistent with SVF syntax. Note that onTAP allows C-like flow control expressions to be embedded within SVF files and that these expressions also use exclamation marks. onTAP distinguishes the two based on context.

As found in the onTAP folder on your computer:

Example of a User Defined IDCODE Test for Three Devices , U2,U3,U4( see onTAP/examples/UserDefinedTests/ idcode_batch.txt).

!Begin here….

create svf c:\bsdapps\UserDefined\idcode.svf; ! the following user statements will be placed in this SVF file

! onTAP uses the declarations between the begin chain and end chain lines to define the chain and to associate a BSDL file with each

! circuit location in the chain.

begin chain;

U2 = xc9536xl_pc44;

U3 = ispLSI2032VE;

U4 = 3032AL44;

end chain;

BIT_STRING u2_version, U2_part_num, U2_manuf_id, U2_required; // declare string variables for U2 IDCODE fields

BIT_STRING u3_version, U3_part_num, U3_manuf_id, U3_required; // declare string variables for U3 IDCODE fields

BIT_STRING u3_version, U3_part_num, U3_manuf_id, U3_required; // declare string variables for U4 IDCODE fields

BIT_STRING u4_version, U4_part_num, U4_manuf_id, U4_required; // declare string variables for U4 IDCODE fields

BIT_STRING zeroes;

state reset; ! place chain defined in TAPMAP in reset state

begin scan; ! onTAP creates one SIR scan in SVF file for U1,U2,U3

U2=IDCODE; ! if the BSDL file is in the folder, onTAP will find the opcode for U2’s IDCODE instruction

U3=IDCODE;

U4=IDCODE;

end scan;

! When compliled with Tools/Compose SVF, onTAP uses the declarations between begin scan and end scan lines

! to create an SIR scan that loads the IDCODE instructions.

U2_version = "XXXX"; ! IDCODE version field from U2’s BSDL file

U2_part_num = "1001011000000010"; ! part number

U2_manuf_id = "00001001001"; U2’s manufacturer’s id

U2_required = "1"; // required by BSDL spec

U3_version = "0001"; ! IDCODE version field from U3’s BSDL file

U3_part_num = "0000001100000001"; ! part number

U3_manuf_id = "00000100001"; U3’s manufacturer’s id

U3_required = "1"; // required by 1149.1 spec

U4_version = "0001"; ! IDCODE version field from U4’s BSDL file

U4_part_num = "0111000000110010"; ! part number

U4_manuf_id = "00001101110"; U4’s manufacturer’s id

U4_required = "1"; // required by BSDL spec

zeroes = "00000000000000000000000000000000"; // 32 zeroes

! TDI definesTest Data In and TDO defines Test Data Out.

! The strings in the TDO expression will be concatenated. LSB is on the right.

begin scan;

U2 = TDI(zeroes) TDO(U2_version+ U2_part_num+ U2_manuf_id+ U2_required); !concatenate BIT_STRINGS to form TDO string

U3 = TDI(zeroes) TDO(U3_version+ U3_part_num+ U3_manuf_id+ U3_required);

U4 = TDI(zeroes) TDO(U4_version+ U4_part_num+ U4_manuf_id+ U4_required);

end scan;

! When compiled with Tools/Compose SVF, the declarations between begin and end scan will be compiled into

! an SVF SDR scan.

! Examples of test statements that may be applied follow. onTAP will extract the measured value from SDR scans and will update

! BIT_STRING values so that they can be used in control flow branch expressions as shown below.

if ( U3_part_num != "0000001100000001" )

{

MESSAGE_PAUSE("U3’s IDCODE part number, %%s, is incorrect. Should be "0000001100000001"",U3_part_num);

}

if ( !(U2_part_num & "010"))

{

MESSAGE("bit 1 in U2’s part number reads low but should be high");

}

if ( U3_part_num != "0000001100000001" )

{

MESSAGE("U3’s part number reads %%s, but should read 0000001100000001", U3_part_num);

}

if ( FAIL )

{

MESSAGE("IDCODE test fails");

}

User defined script files may be compiled into SVF files by selecting the Compose SVF File menu item from the Tools menu.

When the command file, idcode_batch.txt, is called a new SVF file, IDCODE.SVF is created. Instructions such as “state reset;” are transferred directly into the new SVF file. onTAP compiles chain-wide SIR and SDR instructions based on a list of SIR and SDR instructions for each device in the target chain. SIR and SDR statements for the first device in a chain are listed first and statements for the last device are listed last.

A “log scan data on;” statement enables all scan-in and scan-out data to be captured in the scandata.txt file.

User Defined Instruction Statements

Statement	Use
create filename.svf;	Begin ceation of a new SVF file.
state state_name	Sequence TAP to designated state.
begin scan;	Begin steps that will be compiled into an SIR or SDR scan .
end scan;	End steps that will be compiled into an SIR or SDR scan .
BIT_STRING_name;	Declare string variables.
LogScanDataOn()	Enables logging of scan data to the project folder file scandata.txt.
LogScanDataOff()	Disables logging of scan data to the project folder file scandata.txt.

The Importance of Testing for Mid-State/Resistive Shorts

admin — Mon, 02 Nov 2009 17:10:01 +0000

Mid-state shorts are a major problem that often goes undetected by typical boundary scan connectivity tests is mid-state/resitive shorts. Flynn Systems recognized this "hole" in boundary scan testing and was the first boundary scan test company to test for mid-state shorts, improving test fault coverage.

How onTAP Detects and Diagnoses Mid-State Shorts

Mid-state shorts are bridging faults that result in a mid-state voltage level rather than a hard low or high level. In our experience at Flynn Systems when working with customers, we have found the condition occurs where short circuits exist:

1. between some boundary-scan pins on FPGA devices when only one boundary scan pin is present on a PCB net
2. across pins on resistor networks where the resistors lie between the shorts fault and scannable pins, and again on nets that have only one boundary-scan pin

Mid-state shorts, like any bridging fault, can result in system level applications failures if not detected and cleared. The difficulty is that these shorts will not be detected by traditional boundary scan shorts detection algorithms where zero or one logic levels must be detected. The reason is that at the capture cell on single-pin nets, the capture value is equal to the value being actively driven from the same pin.

In the case of the resistor network, it is easy to see how the resistors can isolate the capture value from the value measured at the physical short. In the case of the FPGA pins the reasons are not quite so clear, but apparently sufficient impedance exists between the bidirectional cells and physical pins so that the input cell sees the value driven from the drive cell, not the value measured at the physical short. Again, the capture value is equal to the expected value, producing a PASS.

How can Mid-State Shorts be Detected?

As might be expected, MID-STATE shorts can be detected by a test pattern that uses tri-state, high impedance values, Z, in combination with zero and one values. One difficulty, however, is that since Z is a passive condition, this approach is likely to result in unpredictable numbers of false failures. Another problem is that the number of potential test scans required can be quite large.

onTAP addresses these difficulties in several ways. First, to achieve a manageable number of test patterns, standard Wagner test popular in boundary scan testing and known for their compactness and effectiveness, are employed. But instead of using only 0-1 test patterns, 0-Z and 1-Z patterns are also used. This is effective and will detect the shorts, but will inevitably also produce false failures.
To deal with the false failures, onTAP actively interrogates all indicted net combinations at run time with a more exhaustive
0-1-Z pattern that eliminates false failures but indicts any MID-STATE shorts
conditions.

PC Based Parallel Test

admin — Fri, 30 Oct 2009 17:03:27 +0000

Ontap_parallel.exe can be used to simultaneously run test suites on multiple PC boards using the onTAP DLL. Parallel board testing must be enabled for the DLL license. Testing is fastest on a multiple processor PC , particularly where one core processor is available for each board. For example if four PC boards are being tested in parallel, then a quad core processor is recommended so that the time to test four boards is about the same as that required to test one board.

Procedure for Running Tests in Parallel

Create a separate folder for each board to be tested and in the folder place all of the tests that will be run for a board.

Launch an ontap_parallel.exe for each board to be tested, and for each instance of ontap_parallel.
exe, browse to a folder with the tests for a designated board. In the SVF Files list, check the SVF files that will be run for the board.

Return to the first instance of ontap_parallel.exe and check the boards that you wish to run in the Board list.

Click Run Checked Board Folders to run the tests for one or more folders. Test results are left in the .test and .fail files for each test in each folder. The test and diagnostic messages can be seen on the screen by selecting, as opposed to checking, a board and then selecting an SVF file.

JTAG.TECT Reviews onTAP JTAG System

admin — Thu, 29 Oct 2009 20:10:21 +0000

Written by: Dr. Ami Gorodetsky of JTAG.TECT

Please follow this link for the original Russian:
http://www.jtag-test.ru/JTAGUniversity/articles/12-PE_6_2009.php

View Dr. Ami Gorodetsky’s blog:
http://moodle.cs.huji.ac.il/cs08/course/view.php?id=67703

In the 7^th paper of our “JTAG and DFT Basics Tutorial” series we had briefly examined the software basics of US based Flynn Systems’ (www.flynn.com ) onTAP Boundary Scan system that is intended for the JTAG test development, execution, and debugging, but the system hardware was not mentioned in the paper. In this sequential 12^th paper of the series we will overview the hardware of this very popular JTAG test system that is in worldwide usage for the JTAG-based test and in-circuit programming and flash burn-in stations, both in the lab environment and on the production facilities.

One of the noticeable and special features of the onTAP, which fairly distinguishes it from the hardware of competitor’s systems, is the surprising simplicity and mobility of the onTAP interface and, correspondingly, its low price. The onTAP hardware consists of the following three groups: two interface USB-adapters (the 6 MHz FS-9160 and the 30 MHz Dual Channel FS-9165), the FS-9180 TAP Serializer and GPIO Board, and a series of parallel JTAG-cables of different vendors (Xilinx, Altera, Lattice, etc.) that onTAP also supports. Designation of both USB-adapters, connected between a user’s PC and the UUT, is to support the operating voltages in the range of 1.8V to 5V, to increase the loading capacity and noise protection of the JTAG bus, and therefore, notably increasing the permissible distance between the PC-based test station and the UUT without any additional TCK frequency constraints.

The USB interface adapters together with the onTAP software allow for an easy and very mobile platform, without any noticeable limitations, to enlarge a quantity of JTAG chains utilized in the test, identical or different. In other words, the JTAG test preparation for a printed circuit board that contains n JTAG chains requires to have n FS-9160 adapters, or n/2 FS-9165adapters. With the usage of the FS-9180 TAP Serializer and GPIO Board the number of adapters can be substantially reduced. The same hardware setup (with the FS-9180 TAP Serializer or without it) also supports the simultaneous testing of n identical printed circuit boards with one or several JTAG chains; this situation is frequently encountered during the testing of similar printed circuit boards in mass production.