onTAP Boundary Scan Software Now Supports IEEE 1149.6

Common tri-state control cells are groups of pins on a common net.  Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.

Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below. 

In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.

This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.

How onTAP Detects and Diagnoses Mid-State Shorts

Mid-state shorts are bridging faults that result in a mid-state voltage level rather than a hard low or high level. In our experience at Flynn Systems when working with customers, we have found the condition occurs where short circuits exist:

1. between some boundary-scan pins on FPGA devices when only one boundary scan pin is present on a PCB net
2. across pins on resistor networks where the resistors lie between the shorts fault and scannable pins, and again on nets that have only one boundary-scan pin

Mid-state shorts, like any bridging fault, can result in system level applications failures if not detected and cleared. The difficulty is that these shorts will not be detected by traditional boundary scan shorts detection algorithms where zero or one logic levels must be detected. The reason is that at the capture cell on single-pin nets, the capture value is equal to the value being actively driven from the same pin.

In the case of the resistor network, it is easy to see how the resistors can isolate the capture value from the value measured at the physical short. In the case of the FPGA pins the reasons are not quite so clear, but apparently sufficient impedance exists between the bidirectional cells and physical pins so that the input cell sees the value driven from the drive cell, not the value measured at the physical short. Again, the capture value is equal to the expected value, producing a PASS.

How can Mid-State Shorts be Detected?

As might be expected, MID-STATE shorts can be detected by a test pattern that uses tri-state, high impedance values, Z, in combination with zero and one values. One difficulty, however, is that since Z is a passive condition, this approach is likely to result in unpredictable numbers of false failures. Another problem is that the number of potential test scans required can be quite large.

onTAP addresses these difficulties in several ways. First, to achieve a manageable number of test patterns, standard Wagner test popular in boundary scan testing and known for their compactness and effectiveness, are employed. But instead of using only 0-1 test patterns, 0-Z and 1-Z patterns are also used. This is effective and will detect the shorts, but will inevitably also produce false failures.
To deal with the false failures, onTAP actively interrogates all indicted net combinations at run time with a more exhaustive
0-1-Z pattern that eliminates false failures but indicts any MID-STATE shorts
conditions.
 

Procedure for Running Tests in Parallel

Create a separate folder for each board to be tested and in the folder place all of the tests that will be run for a board.

Launch an ontap_parallel.exe for each board to be tested, and for each instance of ontap_parallel.
exe, browse to a folder with the tests for a designated board. In the SVF Files list, check the SVF files that will be run for the board.

Return to the first instance of ontap_parallel.exe and check the boards that you wish to run in the Board list.

Click Run Checked Board Folders to run the tests for one or more folders. Test results are left in the .test and .fail files for each test in each folder. The test and diagnostic messages can be seen on the screen by selecting, as opposed to checking, a board and then selecting an SVF file.

(text version – download PDF version here)

Escape Communications asked Flynn Systems to help them tackle the challenge of embedding boundary scan tests into their ATB design through the use of readily available, off-the-shelf firmware in order to minimize customization and engineering development costs.  Escape selected the FTDI 2232D Dual USB UART/FIFO IC chip for the ATB test interface, the same chip Flynn Systems uses in their USB JTAG Test and Programming cable.  Escape and Flynn have both had great success with this particular device due to its versatility and full range of capabilities for test and development purposes.

The Escape solution confines the necessary test equipment to little more than a common high speed A-A USB 2.0 cable, controlling the embedded FTDI chip through Escape’s board design and its own test executive.  The result: “Now we have created a way to easily access the board and perform all the necessary functions for the different devices on the board.  Flynn was easy to work with and open to the idea of embedding a solution,” Pascaru noted.  Instead of having several cables and test and programming pods interfacing with the board, there is one embedded device connected to the test PC via a standard USB 2.0 port.  

From a single test port, a design, test, or manufacturing test engineer can simply plug the board into an onTAP-enabled PC or laptop, and run a complete suite of pre-developed onTAP boundary scan tests.  onTAP’s automated test generation delivers the highest possible fault coverage with a graphical debugging environment that provides pin-level diagnostic messages and detailed test reports. Pascaru is pleased with the outcome of the seamless integration of onTAP with Escape’s Automated Test Board.  The comprehensive test results provided by onTAP enable users to identify and repair faults on boards under test more quickly and easily than ever before.

Founded in 1998, Escape Communications provides indoor units (IDUs), high-speed modem modules, and Satcom terminals to commercial telecommunications equipment OEMs and major space and defense contractors.  Escape has developed an extensive portfolio of communications, signal processing, mixed-signal and embedded processor IP that enables them to offer standard product solutions and custom turnkey design services that are both cost-effective and schedule-efficient.  More details can be found at www.escapecom.com.