Flynn Systems » Documentation

Built In Self Test (BIST)

admin — Thu, 19 Mar 2009 21:42:27 +0000

Tests may be defined in script files which may then be translated into executable Serial Vector Format (SVF) files. The general approach is to place all of the required BSDL files into a folder and then to relate the BSDL files to circuit locations in declarations at the beginning of the script file. Once BIT_STRINGS are defined, instruction register scans may be created by simply declaring the instruction names to be used. And data scans can be created by concatenating BIT_STRINGS. String variables may be assigned values and then multiple variables may be concatenated. In addition literal string assignments may be used directly or mixed with variables.

Values are always expressed as binary strings, BIT_STRINGS. If zero and one values are present in a TDO string, the corresponding MASK bits will be set to one. If ‘X’ characters are present in a TDO string, the corresponding mask bits are set to zero.

The following example shows a very literal application of an IDCODE test to a three device chain. Comments, beginning with the ! character, explain the purpose of each statement and are consistent with SVF syntax. Note that onTAP allows C-like flow control expressions to be embedded within SVF files and that these expressions also use exclamation marks. onTAP distinguishes the two based on context.

As found in the onTAP folder on your computer:

Example of a User Defined IDCODE Test for Three Devices , U2,U3,U4( see onTAP/examples/UserDefinedTests/ idcode_batch.txt).

!Begin here….

create svf c:\bsdapps\UserDefined\idcode.svf; ! the following user statements will be placed in this SVF file

! onTAP uses the declarations between the begin chain and end chain lines to define the chain and to associate a BSDL file with each

! circuit location in the chain.

begin chain;

U2 = xc9536xl_pc44;

U3 = ispLSI2032VE;

U4 = 3032AL44;

end chain;

BIT_STRING u2_version, U2_part_num, U2_manuf_id, U2_required; // declare string variables for U2 IDCODE fields

BIT_STRING u3_version, U3_part_num, U3_manuf_id, U3_required; // declare string variables for U3 IDCODE fields

BIT_STRING u3_version, U3_part_num, U3_manuf_id, U3_required; // declare string variables for U4 IDCODE fields

BIT_STRING u4_version, U4_part_num, U4_manuf_id, U4_required; // declare string variables for U4 IDCODE fields

BIT_STRING zeroes;

state reset; ! place chain defined in TAPMAP in reset state

begin scan; ! onTAP creates one SIR scan in SVF file for U1,U2,U3

U2=IDCODE; ! if the BSDL file is in the folder, onTAP will find the opcode for U2’s IDCODE instruction

U3=IDCODE;

U4=IDCODE;

end scan;

! When compliled with Tools/Compose SVF, onTAP uses the declarations between begin scan and end scan lines

! to create an SIR scan that loads the IDCODE instructions.

U2_version = "XXXX"; ! IDCODE version field from U2’s BSDL file

U2_part_num = "1001011000000010"; ! part number

U2_manuf_id = "00001001001"; U2’s manufacturer’s id

U2_required = "1"; // required by BSDL spec

U3_version = "0001"; ! IDCODE version field from U3’s BSDL file

U3_part_num = "0000001100000001"; ! part number

U3_manuf_id = "00000100001"; U3’s manufacturer’s id

U3_required = "1"; // required by 1149.1 spec

U4_version = "0001"; ! IDCODE version field from U4’s BSDL file

U4_part_num = "0111000000110010"; ! part number

U4_manuf_id = "00001101110"; U4’s manufacturer’s id

U4_required = "1"; // required by BSDL spec

zeroes = "00000000000000000000000000000000"; // 32 zeroes

! TDI definesTest Data In and TDO defines Test Data Out.

! The strings in the TDO expression will be concatenated. LSB is on the right.

begin scan;

U2 = TDI(zeroes) TDO(U2_version+ U2_part_num+ U2_manuf_id+ U2_required); !concatenate BIT_STRINGS to form TDO string

U3 = TDI(zeroes) TDO(U3_version+ U3_part_num+ U3_manuf_id+ U3_required);

U4 = TDI(zeroes) TDO(U4_version+ U4_part_num+ U4_manuf_id+ U4_required);

end scan;

! When compiled with Tools/Compose SVF, the declarations between begin and end scan will be compiled into

! an SVF SDR scan.

! Examples of test statements that may be applied follow. onTAP will extract the measured value from SDR scans and will update

! BIT_STRING values so that they can be used in control flow branch expressions as shown below.

if ( U3_part_num != "0000001100000001" )

{

MESSAGE_PAUSE("U3’s IDCODE part number, %%s, is incorrect. Should be "0000001100000001"",U3_part_num);

}

if ( !(U2_part_num & "010"))

{

MESSAGE("bit 1 in U2’s part number reads low but should be high");

}

if ( U3_part_num != "0000001100000001" )

{

MESSAGE("U3’s part number reads %%s, but should read 0000001100000001", U3_part_num);

}

if ( FAIL )

{

MESSAGE("IDCODE test fails");

}

User defined script files may be compiled into SVF files by selecting the Compose SVF File menu item from the Tools menu.

When the command file, idcode_batch.txt, is called a new SVF file, IDCODE.SVF is created. Instructions such as “state reset;” are transferred directly into the new SVF file. onTAP compiles chain-wide SIR and SDR instructions based on a list of SIR and SDR instructions for each device in the target chain. SIR and SDR statements for the first device in a chain are listed first and statements for the last device are listed last.

A “log scan data on;” statement enables all scan-in and scan-out data to be captured in the scandata.txt file.

User Defined Instruction Statements

Statement	Use
create filename.svf;	Begin ceation of a new SVF file.
state state_name	Sequence TAP to designated state.
begin scan;	Begin steps that will be compiled into an SIR or SDR scan .
end scan;	End steps that will be compiled into an SIR or SDR scan .
BIT_STRING_name;	Declare string variables.
LogScanDataOn()	Enables logging of scan data to the project folder file scandata.txt.
LogScanDataOff()	Disables logging of scan data to the project folder file scandata.txt.

Managing Differential I/O Pairs

admin — Tue, 17 Mar 2009 17:08:37 +0000

To manually specify differential pairs, proceed through test development, to the SETTINGS PAGE and click the Identify Differential Pairs button.

Automatic Detection

onTAP automatically recognizes and accounts for differential I/O pairs as they are declared in the BSDL.

Specify Differential I/O Manually

If your application does not declare differential I/O pins in the BSDL file, you can declare them within onTAP prior to test generation so that they are properly controlled in the test vectors.

Follow the on-screen instruction on the Create Differential Signals page and Transmitter and Receiver Pins page.

onTAP stores the differential I/O pin declarations in DiffPairsList.txt so that you can also edit the file with your preferred text editor. We recommend TextPad.

Eliminating the “Ground Bounce” Effect with JTAG Test

admin — Tue, 10 Mar 2009 14:18:42 +0000

When large numbers of outputs switch simultaneously, they can cause intermittency with your test due the ground bounce effect. onTAP lets you control this problem by giving you control over how many outputs switch during a single test scan, as shown below:

Boundary Scan Test Fault Insertion

admin — Tue, 10 Mar 2009 14:04:53 +0000

Use this function to:

Check the fault coverage of your test for a specific fault condition.
Insert an open fault without modifying your board or test fixture.
Validate that your test is working as expected.

How to Insert Faults

1. Create a file FaultInsert.txt in your test project directory.

2. Add fault declarations to the FaultInsert.txt file as shown below. A sample file with syntax examples can be found in the /onTAP program directory.

	open u6.15;	// pin will be open to all signals
	open u9.12,u12.8;	// multiple pins will fail to capture other pins’ signals
	stucklow u6.18;	// pin and net are stuck low
	stucklow u20.a5;	// all pins on net ADDR14 will be measured low
	short u3.8 u2.10;	// shorts nets of pins in list, low values prevail.
	drivelow u17.6;	// always drive pin to a low value
	drivehigh u13.18;	// always drive pin to a high value
	drivez u7.a2;	// always drive pin to a high impedance
	measurelow u20.9;
	measurehigh u67.3;

3. Run the project’s SVF file from the onTAP Test Screen.

When onTAP detects a FaultInsert.txt file in your project folder, it posts a message so that when you run the the test, diagnostic messages corresponding to the inserted fault expressions are displayed.

onTAP Supported Netlist Readers

admin — Mon, 09 Mar 2009 17:48:38 +0000

Available Netlist Readers for onTAP Boundary Scan Software
Netlist Format	File Extensions	Comments
GenRad	.CKT	For ATE at Board Test
GenCad	.NET
EDIF	.EDN or .EDF
Allegro Format	.NET	ViewLogic source. Characterized by $PACKAGES and $NETS expressions.
BOARD STATION	.NET and .PKG	Net and package files must have the same root name.
Cadstar	.NET + .FRS
Cadstar RINF Output	.FRS
Cadence (Concept)	.DAT
Cadence PST	.DAT or .NET
CadSOFT (EAGLE Version)	NETS.ASC + MATERIAL.ASC	Requires three source files, each with the filename extension DAT. One file must have header text that includes the expression “"FILE_TYPE=LIBRARY_PARTS;", One file must have header text that includes the expression "FILE_TYPE = EXPANDEDNETLIST;", And one file must have header text that includes the expression "FILE_TYPE = EXPANDEDPARTLIST;"
FabMaster	NETS.ASC + MATERIAL.ASC
Isis	.SDF
ViewLogic Generic Format	.NET + .PKG
PADS POWERPCB	.ASC or .NET	Characterized by PART and SIGNAL expressions.
PADS PXR Format	.PXR
Mentor Neutral	.NEU	PC Easy
OrCad	.NET	Characterized by expressions such as “(compins”,”(net”,(node”.
PC Easy	.NET
Protel	.NET
Protel2	.NET
Agilent’s BOARD
Teradyne’s IPL.DAT	.DAT	For ATE at Board Test
Teradyne’s Victory	.CDS	For ATE at Board Test
Zuken CR5000	Multiple .NET
Zuken Visula	.REP + .LST	.REP file includes netlist and .LST file includes component list.

onTAP Supported Memory and Flash Models

admin — Fri, 06 Mar 2009 19:43:01 +0000

This table shows the variety of flash and memory cluster models currently available. These models are made using the high level DTS language, making the models flexible, and re-usable. If you do not see your particular model, please contact support.

Model Types

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FLASH RAM Dual Port SDRAM DDR RAM DDR2

FIFO SODIMM Serial EPROM EEPROM I²C Discrete Components

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FLASH	Package Type (if available)
28f128_program
28F128J3A
iCORE_28f128_program
28F128J3C150_rev
28F128_byte 28f128_program 28f128_test 28f128_verify 28f128_program_pins 28f128_verify_pins
28f160_FlashID 28f160_prog 28f160_test 28f160_verify
28F320J3 28F320J3_byte
28F640J3_byte_prog 28F640J3_byte_test 28F640J3_byte 28F640J3_byte_trial 28F640J3_byte_trial
28f640w18_test_id. 28f640w18_test
e28f640
GE28F640W18_BB_UREM GE28F640W18_CMC_UREM
s29al016_48ball_prog s29al016_48ball_veri
29gl064m_prog 29gl064m_program_48pin 29gl064m_test_48pin 29gl064m_verify_48pin
29gl128_64bga_prog 29gl128_64bga_veri
29gl128m_56pin. 29gl128m_56pin_prog 29gl128m_56pin_veri
29glm_prog 29gl256m_56pin 29gl256m_56pin_erase 29gl256m_prog 29gl256m_prog 29gl256m_sect 29gl256m_ver 29gl256m_verify_56pin 29gl256m_verify
29LV320	32MEG 2/4M x 16/8-Bit 48 PIN TSOP
S29LV040B	4 MEG 512 x 8-Bit 32 PIN PLCC
29LV065D	64 MEG 8M x 8-Bit 48 PIN TSOP
29LV400BB 29LV400BB_byte
29PL032
AM29DL323	32 MEG 4M x 8-Bit CMOS 3.0 Volt.48 PIN TSOP
AM29DL640G	64 MEG 8M x 8-Bit CMOS 3.0 Volt.48 PIN TSOP
AM29F800BB-120	1 MEG x 8-Bit/512 K x 16-Bit CMOS 5.0 Volt.48 PIN TSOP
AM29800BB-120
AM29LV256MH	256 MEG 16MEG x 16-Bit CMOS 3.0 Volt.56 PIN TSOP
AM29LV400B	4 MEG 512 K x 8-Bit/256 K x 16-Bit CMOS 3.0 Volt.48 PIN TSOP
K9F5608	256 MEG 32M x 8-Bit NAND Flash 48 PIN TSOP
M29W160_Auto M29W160_word
M29W640FB70N6E
M581W064
MX29LV320_BALL	32MEG 2/4M x 16/8-Bit 48 PIN TSOP
SST49LF080A
SST39VF6401B
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RAM	Package Type
IDT71416
CY62126
CY62128
CY62168
CY7C1021
CY7C1041
CY7C128
CY7C1380
CY7C1338G	TQFP 100
CY62128
K6X8016T3B
K6R4016V1
TMS626162
IS61VPS25672A
K6R4016V1
K6X8016T3B
TMS626162
WS128K32V
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Dual Port	Package Type
IDT7028	TQFP
IDT70V9279
IDT7025	PLCC
IDT72361	TQFP
512KX	18X8
512KX	16X32
128KX	36X4
256KX	36X8
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SDRAM	Package Type
EDD1216aata
EDD1216aata	TSOP 66
EDD1216aata	mod2
EDD1216aata	mod3
HYB39s256160t
HYB39s256160t	no clk
IS42S16160B	TSOP 54
K4e171611d
K4S561632	TSOP 54
K4s81632	TSOP 5
MT48LC8M16	TSOP 54
MT48lc8m16lf
MT48lc8m32	bga
MT48lc8m32	bga
MT48lc8m32	TSOP
MT48lc8m32	TSOP 86
MT48lc16m16l2	SDRAM w/Clock
MT48lc16m16l2	16MEG x 16 x 4 SD Ram
MT48lc16m16l2	pll
MT48lc16m16a2
MT48lc16m16	TSOP 54
TMS626162A	SDRAM 20-PIN
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DDR RAM	Package Type
MT46M64	16MEG x 8 x 4 DDR BGA
mt46v16	TSOP 66 32MEG x 16
MT46V16M16	TSOP 66 16MEG x 16 x 4
MT46v16m16	no clk
MT46v16m16	4MEG X 16 X 4
MT46v16m16	64 Meg 8 Meg X 16
MT46v32m16	TSOP 66
MT46v32m16	TSOP 66 B
MT46V128

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DDR2	Package Type
HYx16T512xx	bga 60m8
hyb18t512t	bga 84
k4t1g164qa	numeric pins
k4t1g164qa	bga 32MEG x 16 DDR2 SDRAM
k4t1g164qa	bga 1Gb DDR2 SDRAM
mt16htf12864h
MT47H32	bga
mt47h32m16	bga 84
mt47h64m16	bga 64MEG x 16 DDR2 SDRAM
mt47h64m16	bga 32MEG x 16 DDR2 SDRAM
*MT49H8M36
k4t1g164qa	bga
k4t1g164qa	numeric pins

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FIFO	Package Type
72V3690
IDT72V245
IDT723631
IDT72245
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SODIMM	Package Type
MT8LSDT1664
MT8LSDT3264
HYS64D32020
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Serial Eprom & EEPROM	Package Type
AT24C01B_WRITE
AT24C02
AT24C04
AT24C16
at24c256_prog
at24c256_veri
AT93C46
AT93C66	4K FLASH 4 PIN
EPCS4	4 MEG FLASH 8 PIN
EPCS16	16 MEG FLASH 16 PIN
M25P32
M25P128
M24_C08	Two-wire Serial EEPROM
M25P64
M25P128
MAX7311	I2C 2-wire-interfaced expander 24 PIN TSOP
W25P64
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I²C	Package Type
PCA9551	8 bit I2C-bus LED driver
TM162 TIANMA	LCD DISPLAY 14 PIN
AT24C01B	Write
AT24c256	Prog
AT24c256	Verify
M24	C 08 prog
M24	C 08 verify
MAX7311	Test
MAX7311	Test Port
PCA9551
PCA9551	I2C

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Discrete Components
65HVD10	74FCT16244
74AS641	74AVC16244
74AUC1G126	74LVT16244
74AUC34	74LVTH16244
74AVC16835	74ALB16244
74S244	SN74ALB16244
SN74AUCH240	74LVT162244
74LVTH241	74FCT162244
74LS244	74LVTH162244
74LVT244	74LCX16245
74F244	74FCT16245
74HC244	74ABT16245
74AS760	74AVC16245
74LS245	74ALVCH16245
74LVT245	74LVTH16245
74F245	74ABT16640
74HC245	74ABT16500
74ABT16500	74CBTD3384
74ALVC16334	74CBT3257
74ALVC162344	74fct162245
74AS641	74LVTH162245
74AVC8T245	74FCT162245
74LVC1T45	74LCX162245
74CBT3257	74LVCH16501
74CBTD3384	74ABT16373
74FCT3807	74LVCH32225A
74LCX16244	74LVC2G34
74LCX16245	74S241
74LCX162244	74S373
74LCX162245	74S573
74LS14	7SZ125
74HC04	7SZ126
74LVC14	ADG884_SEL0
74S244	ADG884_SEL1
74LS245	DM74S540
74LVC257	DS29LV010
74LVCH32225A	DS29LV040
74LVCH32973	DS92LV090A
74LVTH32373_BGA9	FCT3807
74LCX32245	FDG6303N
74LVCH32973	GTLP2T152M
74LVTH16543	GTLP8T306
SN74LVCC3245a	ICS83940
74SSVT32852	IDTQS3VH244PA
74LVT125	IDTQS3VH257
74LVC125	IDTQS3861
74LS125	IRF7210
74HCT125	NC2Z00SOT23
74HC125	NC2Z04SOT23
74LVTH125	NC2Z05SOT23
74LVT126	NC2Z08SOT23
74LVC126	NC2Z14SOT23
74LS126	NC2Z32SOT23
74HCT126	NC7SZ66
74HC126	NC7SZ126
74LVTH541DW	OHMx4
74LS541	LOW_OHMx4
74HCT540	HIGH_OHMx4
74LVTH540DW	OHMx8
74HCT541	OHMx8×1
74HCT1G126	LOW_OHMx8
74LVC1G3	HIGH_OHMx8
74LVTH16543	PI3A125
74LVC573	QS3VH257
74LCX16244	QS3VH257Q
74257	RP8P1X2
74LVC257	RP10P1X10
QS532805BQ	RP10P1X2
RN10×2COMMON	RP16P1X16
RP4X1COMMON	RP16P1X2
RP8X1_6_COMMON	RT140_C_
RP8X1COMMON_PLUS	SN74LV157AD
RP13X14_COMMON	SN74LVTH2245
RP100X4	SN74LC1T45
RPCK_22_8P	SN74CB3T16211
RP8P1X8	tm162lcd
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