A QUICK REFERENCE GUIDE TO BOUNDARY SCAN TERMS

BIST: Built-In Self-Test, sometimes controllable via boundary scan

BOARD NETLIST: Files that show the connections between devices on a circuit board and the probe access to circuit nets. Examples: GenRad CKT, Agilent Board, Teradyne IPL.DAT

BOUNDARY REGISTER: A network of register cells linking the TDI and TDO TAP pins. This network provides access to package pins and to system circuits.

BOUNDARY SCAN: A test and access method for electronic devices based on specification IEEE. Std 1149.1a - 1993. Boundary Scan employs scan registers which may operate in system or test mode at each system pin. The boundary scan circuit is controlled by a Test Access Port (TAP) which has four required pins and one optional pin.

BSDL: Boundary Scan Description Language is based on the IEEE 1149.1 standards. BSDL files provide a hardware description language of boundary scan circuits, and most contain the filename extension .bsd or .bsdl. BSDL is a subset of VHDL (Verilog Hardware Description Language).

BYPASS: A boundary scan instruction that allows test data to go through a device and to bypass the boundary register.

CHAINS: A series of one or more boundary scan devices linked from the TDO pin on one device to the TDI pin on another device comprise a chain. Multiple chains may be found on a board or in a system configuration.

CHAIN FINDER: onTAP's process of automatically locating boundary scan device chains on a board under test.

CLUSTER TEST: An onTAP method that allows non-JTAG memory devices to be tested from boundary scan devices when pin access is available. Cluster Test models are written in a high level C-like language. These models are resuable and may be modified for application-specific conditions..

DISABLE: An in-circuit test technique of electrically isolating a device under test (DUT) by applying input signal patterns that turn off the devices that interact with the DUT.

EDIF NETLIST: Electronic Data Interchange Format, is a netlist for a circuit within a device or between devices.

EXTEST: A boundary scan instruction for interconnect test.

FS-ATG: Flynn Systems' ATG tool for programmable logic.

GUARDS: Boundary scan pins may be set to forec or test a static value on a net, to "guard" or limit interaction between boundary scan and non-boundary scan circuits.

HIGHZ: Output high impedance condition.

ICT: In-Circuit Testing is the predominant method of automatic test equipment in digital electronic board manufacturing. ICT equipment accesses digital devices on a PCB through a bed-of-nails test fixture. This access allows ICT to test one device at a time while disabling other devices that interact and might cause test conflicts with the device under test.

IEEE: Institute of Electrical and Electronic Engineers, an organization which advances the theory and application of electrotechnology and allied sciences as well as developing standards for the computer and electronics industry

IEEE1149.1: The standards established by the Joint Action Test Group (JTAG) for boundary scan architecture that incorporates TAP for boundary scan testing of complex ICs. These standards, as a whole, have become synonymous with "JTAG test" and "boundary scan test".

INTERCONNECT TEST: A boundary scan test between multiple devices that uses scan patterns, typically Wagner patterns, to check pin-to-pin connections and shorts. onTAP enhances these patterns with its Resistor Network Shorts feature

INTEST: A boundary scan instruction that allows parallel test vectors to functionally test through a device and to be transported via boundary scan.

ISP: In System Programming is a technique of configuring programmable logic devices via boundary scan.

JTAG: The Joint Action Test Group was a test standards committee that established the current IEEE 1149.1 standards for boundary scan architecture, incorporating the TAP (Test Access Port). The acronym is now synonymous with the group's output. The terms "JTAG", "boundary scan" and "IEEE 1149.1" are used interchangeably.

JUMPERS: A method of making devices on a board transparent allowing onTAP software to "see" through them, or to manage them so that boundary scan pins interact with one another.

MANFACTURING TEST ONLY: An onTAP feature that restricts the use of the software to the test screens and restricts access to menu items which could alter the tests. It is particularly useful in a manufacturing environment whare a user or developer needs to prevent inadvertent change or alteration of the test files.

MID-STATE SHORTS: See Resistor Network Shorts

NETLIST: A Printed Circuit Board roadmap which lists the device types, circuit locations and their pin-to-pin connections. onTAP supports more than 15 CAD-style board netlists.

NETLIST BROWSER: The Netlist Browser provides the ability to browse through a netlist and at the same time set pin values or observe application signal activity accessed from boundary scan’s SAMPLE instruction

onTAP®: Flynn Systems'affordable, full-feature Boundary Scan ATG tool.

RESISTOR NETWORK SHORTS: onTAP's method of detecting hidden short circuit conditions. Ordinary boundary scan shorts test alogorithms do not detect simple faults such as a short circuit between the pins on a resistor network package when the resistors lie between the fault and boundary scan I/O pins. onTAP has custom algorithms that quickly detect these shorts and accurately reports them.

ScanGuard: onTAP'S method that enhances ICT testing within a boundary scan chain by ensuring that each chain device that is not being tested is disabled.

SOFT JUMPERS : Virtual connections in onTAP software models that join the nets on opposite ends of separating elements such as resistors and buffers.

SVF: Serial Vector Format, This is the principal test output file produced by onTAP's TestGen.

TAP: Test Access Port. Each boundary scan device has a TAP that contains the TAP pins, state machine controller circuit, boundary register, and optional BIST and ISP circuits. The TAP pins are:

• TDI (test data in)
  
• TDO (test data out)
  
• TMS (test mode select)
  
• TCK (test clock)
  
• TRST (test reset){optional}

TEST PATTERN: A sequence of applied input values and expected output values related to a device's I/O pins over a series of test steps.

TRANSPARENT DEVICES: Circuit elements such as resistors and bus transceivers that reside between boundary scan pins may be made "transparent" so that the boundary-scan pins are effectively joined or "jumpered" together.

USER DEFINED TEST: A custom test for BIST and other private BSDL file instructions.