As boundary scan technology grows in popularity, more JTAG compliant devices (1149.1 and 1149.6) are now being included in board design, along with more JTAG chains that often require simultaneous testing.

The great advantage to using onTAP, is that there are no restrictions on the number of devices in a chain that it can test. Using just one onTAP TAP CONNECT JTAG Cable, onTAP can test two chains simultaneously. Testing more than two chains in parallel can be achieved in one of two ways:

1. Multiple TAP CONNECT JTAG cables may be used to test chains simultaneously.
2. Serializing chains can be accomplished using the onTAP GPIO Serializer, a single TAP CONNECT Cable, and merged netlists (a task performed by onTAP).

onTAP will perform several critical tests on your board such as:

• TAP Infrastructure/ID Code Test
• Interconnect Test
• Mid-state/Resistive Shorts
• Incorporating Multi-die devices
• Opens and Shorts Tests
• Pull Up/Pull Down
• I2C Bus Control and Test
• Memory/Flash Test & Programming
• Cluster tests
• 1149.6 – AC Coupled Circuit/Differential Pairs

onTAP requires just three items to begin developing a test:

• BSDL Files for all JTAG compliant devices on the board
• Board Netlist
• An onTAP- TAP CONNECT JTAG Cable

An Overview of Some Tests Performed with onTAP

The first test is the TAP (Test Access Port) test. Since JTAG Boundary Scan is essentially a test instrument built into your board, it is important to check the test instrument before beginning a test. Any infrastructure test through device TAPs (Test Access Ports) accomplishes this and in the case of a fault, alerts where a boundary scan chain is broken.

Once the TAP has been verified, the next test is the Interconnect Test.

A connectivity test, or Interconnect Test, is the foundation of any boundary scan test solution. This test verifies that devices are properly connected to your board with no opens or shorts, especially common with BGAs. onTAP’s automatic test pattern generator (ATPG) generates test patterns to ensure that boards are free of defects including opens, stuck-ats-shorts and mid-state/resistive shorts.

Mid-State / Resistive Shorts – Nasty, Tough to Isolate, Show Stoppers

A major problem that often goes undetected by typical boundary scan connectivity tests are mid-state/resistive shorts. While the typical connectivity tests will locate the short between nets 3 and 4 in the example below, they cannot locate the resistive short which exists between nets 1 and 2. This type of short is a mid-state condition, and is recognized and diagnosed. (See our application note on Interconnect testing for more information.)

Bus Wire – Managing Multiple Outputs on a Net

The onTAP-Specific Interconnect test manages bus wires when multiple outputs are connected to a net. onTAP verifies each pin has the chance to drive the output high and low while all inputs capture values.

Cluster Testing – Accessing, Testing, Programming and Controlling non-JTAG Devices 

onTAP uses the high-level DTS test language (see application note and DTS Programming Manual to learn more about this dynamic, C-Like, reusable language) to develop reusable test models for testing connectivity between scan devices and non-scan devices such as DDR2, SRAM, SDRAM, and FLASH. onTAP’s Cluster Test also provides a means to program FLASH memory and configure logic.

For more information regarding onTAP or Boundary Scan, contact Flynn

systems at (603)-598-4444 or visit the website at www.flynn.com.

Many newcomers to JTAG start their first projects knowing only that boundary scan testing is a requirement for new board design. The specifics of boundary scan, details of test strategy, or expected results are for many, an uncharted territory. In fact, most newcomers to boundary scan testing don’t know what questions to ask or how to get started.

If you find that you are in a similar predicament, with a deadline for completing a boundary scan project looming ahead, help is just a phone call away. Flynn Systems is always available to discuss boundary scan in general, your project in particular, and how onTAP® can help you reach your goals. Flynn Systems offers a comprehensive suite of JTAG tools to meet your boundary scan testing needs, and we are always available to answer your questions, concerns, and inquiries regarding what JTAG is and how it can help you 

A Brief History of Boundary Scan Testing

Boundary scan or the boundary scan test is also known as JTAG test or 1149.1. Joint Access Test Group (commonly referred to as JTAG) is a consortium of engineers from a multitude of electronics companies worldwide that formed over twenty years ago to meet the cries and pleas of standardization that the market was lacking. JTAG developed a standardized architecture for testing surface-mount devices applied to denser PCBs (Printed Circuit Boards), a test system commonly dubbed as JTAG or JTAG testing.

In the early 1980s, most PCB testing was achieved using the in-circuit bed-of-nails testers, which generally required physical access to all the devices on the board. This in-Circuit (IC) bed-of-nails technique, provided an efficient and affordable method of testing boards. However, to meet the growing demands of miniaturization, denser (or layered) printed circuit boards began to dominate the market. This posed a huge problem for testing the electrical connectivity between devices, because board density and complex layering prevented the IC pins from being physically probed. Adding to this initial problem was the fact that real estate on boards was becoming a premium: the demand called for more devices with more information on smaller boards. Chip manufacturers met that demand with surface-mount technology.

As good as that was for shrinking technology, surface-mount packaging added complexity to the whole test process, not to mention board layout. Board design layout now had to provide test points for the bed-of-nails fixtures. Adding test points added noise to the board being tested, which created more complexity, more headaches, more delays and more financial cost. Without adding costly test points, access to IC pins could no longer be counted on and engineers as well as chip manufacturers had no set of standards by which to design, build and test. Enter the JTAG consortium.

The Joint Test Action Group originally began with participation from just European electronics companies in the mid-80s. As they sought to devise a specification for boundary scan testing, North American companies joined in the effort and the consortium gained sponsorship from the IEEE.

By 1990, that specification was ready to become the standard for boundary scan test. It was published as IEEE Std 1149.1 and remains the foundation for boundary scan architecture. In 1994, an addition to the standard was made, which contained the Boundary Scan Description Language, more commonly known as BSDL. The BSDL IEEE supplement to 1149.1 describes the logic content of boundary scan compliant devices.

An Overview of What Boundary Scan does

The boundary scan test architecture provides a way to test interconnects between integrated circuits (ICs) on a board without using physical test probes. It contains cells within a device that can capture data from pin or core logic signals or force data onto pins. The captured data is shifted out and externally compared to other results. Forced test data is shifted into the boundary scan cells. This is all controlled from a data path called the scan path or scan chain.

By allowing direct access to nets, boundary scan can eliminate the need for a large number of test vectors. These test vectors are normally needed to properly initialize sequential logic. The benefits of boundary scan technology were quickly realized through shorter test times, higher test coverage, increased diagnostic capability and lower equipment cost.

Flynn Systems

Flynn Systems Corporation, a boundary scan vendor, offers onTAP, a dynamic PC-based boundary scan test software suite. onTAP Boundary Scan provides a cost-effective test solution which encompasses the entire life cycle of a product from development through production. onTAP Boundary Scan technology offers solutions to handle problems such as:

•    Boards that include components assembled on both sides, burying most of the through-holes, thus making them inaccessible

•    Small-size products that do not have test points, making it difficult or impossible to probe suspected nodes

•    Loss of physical access to fine pitch components, making it complicated to distinguish between manufacturing and design issues

For more information regarding our offers our comprehensive set of JTAG tools, onTAP or Boundary Scan, contact Flynn systems at (603)-598-4444

The boundary scan test architecture provides a way to test interconnects between integrated circuits (ICs) on a board without using physical test probes. It contains cells within a device that can capture data from pin or core logic signals or force data onto pins. The captured data is shifted out and externally compared to other results. Forced test data is shifted into the boundary scan cells. This is all controlled from a data path called the scan path or scan chain.

By allowing direct access to nets, boundary scan can eliminate the need for a large number of test vectors. These test vectors are normally needed to properly initialize sequential logic. The benefits of boundary scan technology were quickly realized through shorter test times, higher test coverage, increased diagnostic capability and lower equipment cost.

While boundary scan testing is frequently used in the production phase of a product, this technology is also extremely beneficial when applied to product design, prototype debugging and field service. Thus, the cost can be incorporated over the entire life cycle of the product.

JTAG defines test logic through an integrated circuit, which provides applications to perform five basic duties:

• Chain integrity testing
• Interconnection testing between devices
• Core logic testing (BIST)
• In-system programming (FLASH Programming)
• Functional testing (DDR, SRAM, FLASH, UART, etc.)

Flynn Systems Corporation, offers onTAP, a dynamic PC-based boundary scan test software suite. onTAP Boundary Scan provides a cost-effective test solution which encompasses the entire life cycle of a product from development through production. onTAP Boundary Scan technology offers solutions to handle problems such as:

•    Boards that include components assembled on both sides, burying most of the through-holes, thus making them inaccessible

•    Small-size products that do not have test points, making it difficult or impossible to probe suspected nodes

•    Loss of physical access to fine pitch components, making it complicated to distinguish between manufacturing and design issues

An example of some of the device types typically tested using boundary scan technology are:

•  CPLDs, FPGAs, processors chained together in a boundary scan path
• Non-boundary scan components such as SRAM, SD-RAM, DDR2, DDR3
• Programmable FLASH
• Series resistors or buffers—making them transparent
• I2C devices

There are critical tests that should be performed to test these devices, such as:

• TAP Infrastructure/ID Code Test
• Interconnect Test
• Mid-state/Resistive Shorts
• Incorporating Multi-die devices
• Opens and Shorts Tests
• Pull Up/Pull Down
• I2C Bus Control and Test
• Memory/Flash Test & Programming
• Cluster tests
• 1149.6 – AC Coupled Circuit/Differential Pairs

For more information regarding onTAP or Boundary Scan, contact Flynn systems at

(603)-598-4444 or visit the website at www.flynn.com.

Our Development team has been busy at work on a new UI for onTAP. We’re all excited about the new look and we’re sure you will like it as much as we do.

We expect to introduce our new and improved onTAP mid-to-late Q1 2013, so stay tuned for updates.

In the meantime, all of us at Flynn Systems wish to thank our customers for all the great suggestions and for sending us your wish list items. We have incorporated many of your requests into onTAP’s new UI.

We wish you all a Happy Holiday Season and we look forward to working with you on your boundary scan projects next year!

The Flynn Systems Team

While not all boundary scan terminology is contained in the guide, there are enough terms to at least acquaint you with some of the most commonly used expressions.

BIST:
Built-In Self-Test, sometimes controllable via boundary scan

BOARD NETLIST:
Files that show the connections between devices on a circuit board and the probe access to circuit nets. Many formats are available, including PADS. CADENCE, EDIF, ALLEGRO, etc.

BOUNDARY REGISTER:
A network of register cells linking the TDI and TDO TAP pins. This network provides access to package pins and to system circuits.

BOUNDARY SCAN:
A test and access method for electronic devices based on IEEE. Std 1149.1a –2001 specification. Boundary Scan employs scan registers which may operate in system or test mode at each system pin. The boundary scan circuit is controlled by a test access port (TAP) which has four required pins and one optional pin (see TAP).

BSDL:
Boundary Scan Description Language is based on the IEEE 1149.1 standard. BSDL files provide a hardware description language of boundary scan circuits, and most contain the filename extension .bsd or .bsdl. BSDL is a subset of VHDL (Verilog Hardware Description Language).

BYPASS:
A boundary scan instruction that allows test data to go through a device and to bypass the boundary register.

CHAINS:
Configuration of multiple boundary scan devices.

CLUSTER TEST:
An onTAP method of applying test vectors through JTAG-capable devices to non-JTAG devices.

DISABLE:
An in-circuit test technique of electrically isolating a device under test (DUT) by applying input signal patterns that turn off the devices that interact with the DUT.

EDIF NETLIST:
Electronic Data Interchange Format, is a netlist for a circuit within a device or between devices.

EXTEST:
A boundary scan instruction for interconnect test.

GUARDS:
Used with constraints, such as forcing a value on a net, to “guard” or limit interaction between boundary scan and non-boundary scan circuits.

HIGHZ:
Output high impedance condition.

ICT:
In-Circuit Testing is a type of automatic test equipment in digital electronic board manufacturing. ICT accesses digital devices on a PCB through a bed-of-nails test fixture. This access allows ICT to test one device at a time while disabling any devices that interact and might cause test conflicts with the device under test.

IEEE 1149.1:
The standards established by the Joint Action Test Group (JTAG) for boundary scan architecture that incorporates TAP for boundary scan testing of complex ICs. As a whole, these standards have become synonymous with “JTAG test” and “boundary scan test” (http://www.ieee.org/index.html).

IEEE 1149.6:
An additional IEEE standard that provides for A/C testing (http://www.ieee.org/index.html).

INTERCONNECT TEST:
A boundary scan test between multiple devices that uses scan patterns, typically Wagner patterns, to check pin to pin connections and shorts.

INTEST:
An instruction that allows parallel test vectors to functionally test through a device and to be transported via boundary scan.

ISP:
In System Programming is a technique of configuring programmable logic devices via boundary scan.

JTAG:
The Joint Test Action Group was a test standards committee that established the current IEEE 1149.1 standards for boundary scan architecture, incorporating the TAP (Test Access Port). The acronym is now synonymous with the group’s output. The terms “JTAG”, “boundary scan” and “IEEE 1149.1” are used interchangeably.

JUMPERS:
When circuit elements, such as resistors and bus transceivers, residing between boundary scan pins are made transparent so that the boundary scan pins are effectively joined together.

onTAP:
Flynn Systems’ Automatic Test Generation suite of Boundary Scan tools.

TAP:
Test Access Port. Each boundary scan device has a TAP that contains the TAP pins, state machine controller circuit, boundary register, and optional BIST and ISP circuits. All conform to the IEEE 1149.1 standards  (http://fiona.dmcs.pl/~cmaj/JTAG/JTAG_IEEE-Std-1149.1-2001.pdf)

TAP pins are:
TDI (test data in)
TDO (test data out)
TMS (test mode select)
TCK (test clock)
and optionally
TRST (test reset)

TEST PATTERN:
A sequence of applied input values and expected output values related to a device’s I/O pins over a series of test steps.

Transparent Devices:
Circuit elements such as resistors and bus transceivers that reside between boundary scan pins may be made “transparent” so that the boundary-scan pins are effectively joined or “jumpered” together.

If you find that you are in a similar predicament, with a deadline for completing a boundary scan project looming ahead, help is just a phone call away. Flynn Systems is always available to discuss boundary scan in general, your project in particular, and how onTAP® can help you reach your goals. Flynn Systems offers a comprehensive suite of JTAG tools to meet your boundary scan testing needs, and we are always available to answer your questions, concerns, and inquiries regarding what JTAG is and how it can help you. But, first…

What Boundary Scan Does

The boundary scan test architecture provides a way to test interconnects between integrated circuits (ICs) on a board without using physical test probes. It contains cells within a device that can capture data from pin or core logic signals or force data onto pins. The captured data is shifted out and externally compared to other results. Forced test data is shifted into the boundary scan cells. This is all controlled from a data path called the scan path or scan chain.

By allowing direct access to nets, boundary scan can eliminate the need for a large number of test vectors. These test vectors are normally needed to properly initialize sequential logic. The benefits of boundary scan technology were quickly realized through shorter test times, higher test coverage, increased diagnostic capability and lower equipment cost.

A Brief History of JTAG Boundary Scan Testing

Boundary scan or the boundary scan test is also known as JTAG test or 1149.1. Joint Test Access Group (commonly referred to as JTAG) is a consortium of engineers from a multitude of electronics companies worldwide that formed over twenty years ago to meet the cries and pleas of standardization that the market was lacking. JTAG developed a standardized architecture for testing surface-mount devices applied to denser PCBs (Printed Circuit Boards), a test system commonly dubbed as JTAG or JTAG testing.

In the early 1980s, most PCB testing was achieved using the in-circuit bed-of-nails testers, which generally required physical access to all the devices on the board. This In-Circuit bed-of-nails technique provided an efficient and affordable method of testing boards. However, to meet the growing demands of miniaturization, denser (or layered) printed circuit boards began to dominate the market. This posed a huge problem for testing the electrical connectivity between devices, because board density and complex layering prevented the IC pins from being physically probed. Adding to this initial problem was the fact that real estate on boards was becoming a premium: the demand called for more devices with more information on smaller boards. Chip manufacturers met that demand with surface-mount technology.

As good as that was for shrinking technology, surface-mount packaging added complexity to the whole test process, not to mention board layout. Board design layout now had to provide test points for the bed-of-nails fixtures. Adding test points added noise to the board being tested, which created more complexity, more headaches, more delays and more financial cost. Without adding costly test points, access to IC pins could no longer be counted on and engineers as well as chip manufacturers had no set of standards by which to design, build and test. Enter the JTAG consortium.

The Joint Test Action Group originally began with participation from just European electronics companies in the mid-80s. As they sought to devise a specification for boundary scan testing, North American companies joined in the effort and the consortium gained sponsorship from the IEEE.

By 1990, that specification was ready to become the standard for boundary scan test. It was published as IEEE Std. 1149.1 and remains the foundation for boundary scan architecture. In 1994, an addition to the standard was made, which contained the Boundary Scan Description Language, more commonly known as BSDL. The BSDL IEEE supplement to 1149.1 describes the logic content of boundary scan compliant devices.

While the JTAG consortium remains active, adding more standards for boundary scan testing, the IEEE 1149.1 standard is the foundation upon which additional standards was built.

Flynn Systems

Flynn Systems Corporation, a boundary scan vendor, offers onTAP, a dynamic PC-based boundary scan test software suite. onTAP Boundary Scan provides a cost-effective test solution which encompasses the entire life cycle of a product from development through production. onTAP Boundary Scan technology offers solutions to handle problems such as:

• Boards that include components assembled on both sides, burying most of the through-holes, thus making them inaccessible
• Small-size products that do not have test points, making it difficult or impossible to probe suspected nodes
• Loss of physical access to fine pitch components, making it complicated to distinguish between manufacturing and design issues

For more information regarding onTAP or Boundary Scan, contact Flynn systems at

(603)-598-4444 or visit the website at www.flynn.com.

• Check the fault coverage of your test for a specific fault condition.
• Insert an open fault without modifying your board or test fixture.
• Validate that your test is working as expected.

Please click the “Download Now” button below to continue with the download.

Current build 4393. Updated May 17, 2013.

Featuring:

Drag and Drop for cluster model association (Flash, Memory, and other non-JTAG devices)!

ShowMe! Finally, accurate pin-level diagnostics for memory cluster test debugging!

IMPORTANT NOTE:

VIEW INSTALLATION INSTRUCTIONS

Please click here to learn more about our Turnkey Boundary Scan Solutions

“This [BLADE Network Research] is the second company I’ve used onTAP at, I’ve been using it for 3 or 4 years. Other vendors I’ve used tended to dismiss my problems or suggest a work around that just hides the problem. Lately I’ve been letting Flynn develop our applications because I just don’t have the time.  That’s another option if you need a boundary scan test but have way too many other testing details to sort out.” F. Roberts ‘Test Engineer’ Blade Network Research

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Thank you for your interest in onTAP Boundary Scan/JTAG solutions and XILINX compatibility.

Once we receive your e-mail, we will e-mail you the documents you have requested.  Please be patient.

Feel free to contact info@flynn.com with any questions about the software and JTAG solutions.

Sincerely,

Flynn Systems

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“onTAP Software includes every feature necessary to develop tests for complex multi-board assemblies without expensive add-ons. Apart from performing interconnect or CPLD/FLASH programming, this software also has the capability of developing custom cluster tests.” A Barnai, SMT Magazine, March 2012. onTAP user since March, 2010

Last week, one of our valued onTAP Software users wrote an article for SMT Magazine describing his past five years of experience using boundary scan as a fundamental and critically important test and programming method.  The article is very much worth reading for the insight into his boundary scan application.  We think the best part, though, is when he outlines how his switch to onTAP  Boundary Scan Software has enabled him to improve his test development strategy and implementation.  According to him, onTAP’s full featured boundary scan solutions have facilitated better, more flexible tests because the software is so robust, and the technical support is responsive and helps him adapt the software to meet his needs.

link to full article – March 2012, pp 40 – 46 http://www.smtonline.com/pages/smtmagazine.cgi.