Flynn Systems

FSC and SSP Partner with Value Added Service Provider Agreement

admin — Thu, 29 Jul 2010 16:06:20 +0000

Nashua, NH July, 2010 – Flynn Systems Corp (FSC), developer of onTAP Boundary Scan Solutions, and Solution Sources Programming (SSP), the test technology leader in strategies and development of Benchtop Boundary Scan, ICT, and Functional Test, have established a new strategic relationship. Flynn Systems’ has made Solution Sources Programming, Inc. their new onTAP Boundary Scan Solutions Value Added Service Provider. Serving both Domestic and International Customers, SSP is located in Northern California (San Jose), SSP provides complete JTAG tutorial and customer consulting, DFT and JTAG test program development support for onTAP in conjunction with its ICT and Functionalservices. To assist SSP in expanding their boundary scan test offerings, FSC is providing a complete suite of onTAP Boundary Scan hardware and software, along with technical support to enable SSP to develop and run comprehensive JTAG tests using onTAP Boundary Scan Series 4000.

Current and potential customers of onTAP Boundary Scan Solutions are encouraged to use SSP as a resource for rapid, responsive, full service test solutions. Ryan Flynn, FSC’s Marketing Manager says, “This is a terrific opportunity for Flynn Systems. We are excited to work with an Industry Leader like SSP, known for helping customers by simplifying test strategies but giving the best overall test solutions. We believe working with SSP offers onTAP users more options and a broader range of test development services. We are confident in their capabilities, in their tests and the high level of customer service they deliver to our mutual customers.”

SSP (www.ssprog.com) is a leading developer and supplier of JTAG test solutions in California across all hardware levels, including device, board, and system. SSP is a team of test experts and engineers. SSP serves as a Benchtop Boundary Scan /JTAG, In-Circuit Test (ICT), and Functional Test support supplier for many diverse industries like High Tech, Medical, Green Tech, Defense to name a few.

Design-For-Testability (DFT) analysis including checking the DFT compliance of customer’s design before board layout. onTAP Boundary Scan/(JTAG) test program development, including on-board programming of CPLD, FPGA, flash, I²C, IEEE 1149.6
ICT test program development for the Agilent 307X and Teradyne TS and 228X testers
Functional test program development and system architecture utilizing Agilent and LabView software/hardware solutions; and incorporating Boundary Scan into functional applications.

Flynn Systems Corp. (www.flynn.com) has provided test, debug, and programming solutions for the Boundary Scan test standard (JTAG IEEE 1149.1 – 6) for over ten years. Their onTAP software package delivers completely automated Boundary Scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-Boundary Scan devices interacting with the scan enabled devices. onTAP’s functionality also includes the capability to program flash devices using only the onTAP USB Test and Programming Cable. Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. Its satisfied customers include Intel, Qualcomm, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona. Flynn Systems’ onTAP provides Boundary Scan services for university research, avionics, defense systems, consumer goods, and medical electronics. It is based in New Hampshire with distributors and partners in Europe and in the Middle East.

onTAP Download Request

Update — Sun, 11 Jul 2010 14:00:04 +0000

Thank you for your interest in onTAP Boundary Scan software.

Please click the button below to continue with the download.

Click here to learn more about our 30MHz Dual Channel JTAG Test and Programming cable.

Now supporting IEEE 1149.6!

Current build 4194. Updated July 23, 2010

MUST READ - IMPORTANT NOTE:
Currently we are developing support for industry standard USB JTAG cables such as the XILINX Platform USB and Altera USB Blaster. In doing so, some routines within onTAP have been altered. For the moment, some users may find that onTAP will not load because the Windows environment does not have the necessary settings to enable onTAP to properly function. Please download this Microsoft® file – http://www.microsoft.com/downloads/details.aspx?familyid=9b2da534-3e03-4391-8a4d-074b9f2bc1bf&displaylang=en (if this link does not work, please copy and paste it into your browser).

"This [BLADE Network Research] is the second company I’ve used onTAP at, I’ve been using it for 3 or 4 years. Other vendors I’ve used tended to dismiss my problems or suggest a work around that just hides the problem. Lately I’ve been letting Flynn develop our applications because I just don’t have the time. That’s another option if you need a boundary scan test but have way too many other testing details to sort out." F. Roberts ‘Test Engineer’ Blade Network Research

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onTAP Build Change Log
Build 4194	Upgrades code related to serial flash programming models
Build 4193	Corrects problem in DTS models when passing in values to subroutines and calling subroutines from subroutines
Build 4192	Usability enhancements
Build 4191	Adds capability to write message strings with variables from within the ShowFail(message) instruction Adds capability to run script-generated SVF files with updated scans based on varying bit string values
Build 4190	Corrects problem updating pin register values in DTS models when running cluster tests in multi-chain applications
Build 4189	Corrects problem setting preload values for 1149.6 AC differential receivers when the pin type is bidirectional Corrects problem setting guards from ProScan on bidirectional differential receiver pins. Corrects problem related to option on Jumpers page to automatically add jumpers for IEEE 1149.6 testing of capacitively coupled devices. Extends capability so that in-line resistors are accounted for
Build 4187	Upgrades User Defined script capabilities
Build 4186	Adds capability to run Play/Record binary files in buffered mode, reducing run time and eliminating program latency while in the Run-Test/Idle state
Build 4184	Updates support for onTAP GPIO Serializer Corrects test generation problem when pins from devices in multiple JTAG chains are used in cluster tests Upgrades handling of unplug-plug events for onTAP USB cables
Build 4183	Adds support for AUG netlist format. Corrects problem showing bit-string message values in user-defined scripts.
Build 4181	Updates User Defined code.
Build 4179	Ensures that pins are alternately selected to drive a net when the pins are joined by low-ohm resistors, providing each pin a chance to drive high and low multiple times.
Build 4178	Allows for use of for-loops in User Defined tests.
Build 4177	Updates Protel netlist translator
Build 4174	Sets preload capture values for to opposite value of expected capture values.
Build 4173	Updates 1149.6 related settings.
Build 4172	Add preload provisions for 1149.6 sample instruction.
Build 4171	Corrects problem related to incorrect test values in multi-chain applications for the vectors following the SAMPLE instruction for some configurations.
Build 4170	Improves usability of ProScan graphical debug environment by adding advanced controls for search, pin level diagnostics, and ease of switching between and running tests.
Build 4166	Improves Reset operation of USB cable when Reset buttons are clicked and when calling Reset from the onTAP DLLs. Adjusts diagnostic message for no-connect pins in the event of stuck-at faults. Upgrades use of EXTEST_TRAIN instruction for 1149.6 AC testing.
Build 4165	Adds pin-wiggle capability in ProScan for 1149.6 AC coupled pins. Upgrades Guards+Attributes tab in ProScan to facilitate setting guards, attributes, recompiling, and rerunning tests from within ProScan. Corrects problem showing test messages for multi-chain applications. Adjusts FabMaster netlist translator code.
Build 4164	Corrects DTS test generation where EXTERNAL pin declarations are used when large numbers of cells with common control cells are present.
Build 4163	Adds screen to view onTAP Network License Manager’s server screen.
Build 4162	Updates for Play/Record feature used when loading configuration files. Updates for licensing and onTAP Network License Manager.
Build 4161	Corrects problem with IDCODE tests resulting from millisecond delay settings in multi-chain tests or when specified on the Settings page.
Build 4160	Includes updates for programming Lattice FPGAs. Upgrades differential pair testing. Reads port groupings of differential pair pins in BSDL files and accounts for all positive and negative side pins using BSDL files and netlist.
Build 4158	Adds Play/Record feature for SVF program configuration files. Play/Record converts SVF files to binary, allowing faster programming. Play / Record can be enabled from the Cables menu for specific SVF files. Ensures that guard constraints in the Browse Circuit view are updated when a guard condition is changed the Vector view
Build 4157	Improves stability in ProScan debugging environment
Build 4156	Enables manual input of text in the License Request Folder Edit box on the Help About page.
Build 4155	Statically links Windows DLLs to enable that user’s have the correct DLLs
Build 4153	Corrects potential false failures in multi-chain applications
Build 4152	Ads stability when generating tests for some multi-JTAG chain applications
Build 4151	Corrects problem writing failure reports from Mfg test screen when Operator, Serial Number, and Unit Type text strings are entered. Adds pin-wiggling capability on Nets screen and ProScan for the Xilinx USB cable
Build 4150	Adds code for Xilinx USB Platform Cable support (Beta).
Build 4149	Adds SAMPLE/PRELOAD instruction as a default in first cluster test scan prior to EXTEST instruction.
Build 4148	Corrects test generation for circuits with shared control cells to ensure that only one driver on a net is active at one time. Moves license file, LogicPinMaps and other files within the onTAP folder to the c:\Flynn Systems Corp\onTAP folder, in order to avoid write protected folders within the c:\Program Files folder. The default installation folder is still c:\Program Files\onTAP. Adds code in preparation of support for the Xilinx USB Cable II.
Build 4146	Improves coverage for handling guards when current limiting is enabled
Build 4145	Corrects problem with current-limiting option. Corrects problem writing serial-number-specific files when testing from the Manufacturing Test screen.
Build 4143	Adds netlist translator support for IPL Wirelist netlists Includes adjustment for the current limiting option
Build 4142	Changes the Scan switch factor on the Settings page to a current limiting switch factor (CLSF). Values greater than one limit the total number of pins that can be active at one time during the opens, stuck-at, and pull resistor tests.
Build 4141	Improves handling of edits to attributes and pin-map model assignments on the non-Scan page.
Build 4140	Adjusts ground bounce switch factor operation for pull-up/down tests. Introduces option to add vectors and extend fault coverage in applications where pins share common tri-state control cells. The option is controlled by the “Alternate drive on pins having common control cells” check box on the settings page and the default setting is enabled. Ensures that all eligible pins alternate drive on nets having multiple scan pins. Corrects problem showing all LogicPinMap models on the non-Scan page.
Build 4139	Ease-of-use adjusments
Build 4138	Revises and extends the manner in which the Save Test Reports option works on the Mfg Test screen
Build 4137	Improves operation of JTAG Chain Auto Detect. Adds support for ground debounce switch factor for pull-up/down tests. Adds protection for test settings in the ProScan environment.
Build 4136	Adds support for return instruction in DTS model subroutines. Updates and expands on-line help.
Build 4135	Adds support for use of local variables within subroutines. Adds corrections for test status messages when stopping a test.
Build 4134	Upgrades test vector generation for ground debounce settings greater than one.
Build 4133	Adds safeguards to prevent problems accessing dot fail files when running onTAP DLLs.
Build 4132	Includes inductors in tests solutions and treats inductors as low impedance resistors. Corrects problem with test generation involving low impedance devices.
Build 4131	Additional corrections made for Test Status text as well as shorts test coverage in applications having bus transceiver models
Build 4130	Corrects test message shown in the Test Status column of the Test screens when the Retries on Fail value is greater than zero and a test failure occurs when multiple SVF files are selected.
Build 4129	Adds loopback cable test, in the Cables menu, for the dual channel 30Mhz cable and restores loopback test for the single channel 6Mhz cable.
Build 4128	Provides additional correction for transceiver management during test generation

Boundary Scan Software Evaluation Download

admin — Sun, 11 Jul 2010 14:00:01 +0000

Thank you for your interest in onTAP Boundary Scan software. Please download and install onTAP Boundary Scan Software on your target machine. Once you install onTAP, open and run the software. This will generate a license.txt file. Please copy this file and e-mail it to license@flynn.com. We will activate your license and return a complete onTAP Boundary Scan Software Evaluation. We will also e-mail you with instructions on how to install and start developing tests with onTAP Boundary Scan Software.

Please click the "Download Now" button below to continue with the download.

Current build 4194. Updated July 22, 2010

onTAP now supports and provides capability for IEEE 1149.6!

IMPORTANT NOTE:
Currently we are developing support for industry standard USB JTAG cables such as the XILINX Platform USB and Altera USB Blaster. In doing so, some routines within onTAP have been altered. For the moment, some users may find that onTAP will not load because the Windows environment does not have the necessary settings to enable onTAP to properly function. Please download this Microsoft® file – http://www.microsoft.com/downloads/details.aspx?familyid=9b2da534-3e03-4391-8a4d-074b9f2bc1bf&displaylang=en (if this link does not work, please copy and paste it into your browser).

VIEW INSTALLATION INSTRUCTIONS

Please click here to learn more about our Turnkey Boundary Scan Solutions

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onTAP Supports IEEE 1149.6!

admin — Fri, 14 May 2010 20:26:45 +0000

As we have promised our users, Flynn Systems continues to develop and add new features to onTAP Boundary Scan Software. These new features vastly improve onTAP’s capability, enabling onTAP users to do more with less. We had been developing support for IEEE 1149.6 for several months, and at the end of April, we were able to fully implement the IEEE 1149.6 standard into the current version of onTAP. It has been rigorously field tested, and we are proud to release it to our user community. Please download the newest version of onTAP, and feel free to begin developing truly complete, robust JTAG tests for your projects with IEEE 1149.6 capability.

onTAP Boundary Scan Software Now Supports IEEE 1149.6

NASHUA, NH May 14, 2010 – Flynn Systems Corp is proud to announce the latest version of onTAP is IEEE 1149.6 compliant. The implementation of IEEE 1149.6 greatly enhances onTAP’s scope and capability, while delivering more JTAG test coverage and power to current and interested onTAP users.

According to Ryan Flynn, onTAP Marketing Manager, “As Xilinx and Altera begin to implement IEEE 1149.6 protocols in their latest designs, including the Virtex 6 and Aria GX devices (respectively), it was increasingly important for us to enable onTAP users with every bit of capability so they could harness the full test potential of these new devices and implement them into their designs. onTAP’s IEEE 1149.6 implementation has been field tested in very intense and rigorous applications with Intel. Intel’s success has been a heck of proving ground for onTAP.”

As implementation of IEEE 1149.1 and 1149.X Boundary Scan testing becomes more widespread, greater flexibility, faster speeds, and smoother operation are needed. Flynn Systems’ commitment to its Customers has always been to keep onTAP a live software by continuing to support, develop, and enhance onTAP tools that capitalize on JTAG test capability. The 1149.6 implementation is another demonstration of Flynn’s commitment to its user base.

onTAP’s new update expands users’ test capabilities, flexibility, and further enhances test fault coverage in a number of ways. Most apparent is the productivity gain achieved by testing to both IEEE 1149.1 and IEEE 1149.6 standards. The IEEE 1149.6 feature enables users to test AC Coupled circuits and differential pairs to the industry standard protocol. Adding these two elements to a test not only increases test fault coverage, but also creates a more robust and reliable test by incorporating additional aspects of the board in the test.

Flynn Systems continues its pursuit of delivering cost-effective, complete, robust JTAG test and programming software packages with attentive and dedicated technical support to its current users and anyone interested in a feature-rich, high-value complete JTAG solution at a reasonable price.

About Flynn Systems:

Flynn Systems began delivering Automatic Test Generation Solutions to the ATE market as FS-ATG in 1986. In late 1999, they transitioned to the boundary scan market with onTAP and have provided test, debug, and programming solutions for the boundary scan test standard (JTAG IEEE 1149.1) for over ten years. Their onTAP software package is designed for completely automated boundary scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-boundary scan devices interacting with the scan enabled devices. onTAP’s functionality also includes the capability to program FLASH devices using only the onTAP USB Test and Programming Cable (HighSpeed included). Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. Its satisfied customers include Intel, Qualcom, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona. Flynn Systems’ onTAP provides boundary scan services for university research, avionics, defense systems, consumer goods, and medical electronics. It is based in New Hampshire with distributors and partners in Europe and Asia.

Those interested are invited to download a free 30 day evaluation software package with full technical support available at www.flynn.com.

Groundhog Day Sale

admin — Tue, 02 Feb 2010 21:30:37 +0000

EVERYTHING YOU NEED

Nashua, NH by-way-of Gobbler’s Nob, Punxsutawney, Pennsylvania – Well, it’s official! The groundhog poked out and saw its shadow. Settle in for six more weeks of winter. The upside is, you have six more weeks to not worry about nice sunny days and walks in the park with sunshine on your face. That means more winter time to dedicate to developing and debugging your projects so when spring does finally arrive, you’re ready to take full advantage of the nice spring weather.

We know you’re busy, but bargains are always welcome. Flynn Systems is announcing its Groundhog Day Special.

Even though we all got the bad news that winter is continuing for six more weeks, we want to give you some good news about boundary scan test tools. When you purchase any onTAP Boundary Scan Software license, we are giving you the option to add another license to your package for FREE*. That’s right, FREE. Buy a development seat for the lab, or an MTO for manufacturing, and get another one for a co-worker. You have your choice of an MTO or DLL.

Act fast, this offer only lasts until the first official day of spring – March 20, 2010

We look forward to hearing from you. Please feel free to contact us to discuss your boundary scan application.

THE SMALL PRINT:

*Free onTAP software offer applies to all quotes generated between Feb. 2 2010 and March 20, 2010 and is limited to one free license per quote. Offer is also limited to either an MTO or DLL. Offer expires on March 20, 2010.

Happy New Year – Welcome 2010

admin — Mon, 18 Jan 2010 17:40:17 +0000

We hope everyone is off to a strong and promising 2010. By all signs, it appears that this year will deliver new innovations and products to the electronics market. We certainly are excited to hear about our customers new projects and are looking forward to sharing our new developments with you through out the course of this exciting new year.

Keep an eye for some major upgrades to the software that are sure to greatly increase test capability, usability, and productivity.

Here’s to a successful and prosperous 2010!

Properly Managing Common Tri-State Control Cells Boosts Fault Coverage

admin — Wed, 16 Dec 2009 20:16:00 +0000

As the boundary scan community continues looking for new ways to improve test procedures and achieve higher and higher fault coverage, we expect the test tools to compensate for shortcomings in silicon devices or board design. We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.

Common tri-state control cells are groups of pins on a common net. Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.

Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below.

In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.

The yellow 0 and 1 characters show drive, or boundary register update, values at each test vector, and the green L and H values show expected boundary register capture values on the vectors following an update.

This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.

This image shows how the test was revised to account for the tri-state pins on the common control cell. The result is a boost in fault coverage, with the added benefit of making the test more accurate.

As explained in the text box in this screen shot, onTAP accounts for the shared cells and adds additional test vectors to ensure pins do not drive simultaneously, allowing for more comprehensive tests that deliver higher, and most importantly, more accurate, test fault coverage.

Accepting New Turnkey JTAG Projects

admin — Tue, 17 Nov 2009 20:58:35 +0000

Flynn Systems wants to let our users know that we are accepting new JTAG / Boundary Scan projects for Q1-2/10

While our standard Technical Support provides assistance with test and development issues, our boundary scan test development services go beyond onTAP technical support services by taking the boundary scan / JTAG test development and debugging off your plate, allowing you to focus your undivided attention on your core business issues as you move through development and prototyping into manufacturing.

Our Boundary Scan Test Development Service is very popular with both existing and new customers. In fact, 4 out of 5 customers who have used onTAP boundary scan test development services once, immediately recognize the cost and time savings, and return within 4 months with another project. By turning over your JTAG / Boundary Scan test development to Flynn Systems, you are able focus on other aspects of your project without being distracted by developing and debugging boundary scan tests.

We ensure that your boundary scan tests are maximized for the highest possible fault coverage, are completely debugged, and are ready for the manufacturing floor, so the end user only has to “press a button.”

We support our tests and we will support you and/or your contract manufacturer by answering questions and bringing all parties involved up-to-speed with boundary scan test and onTAP procedures and reports.

Our test development features:

JTAG TAP infrastructure tests.
Interconnect tests including detection of opens, shorts, stuck-at, bus-wire, pull-up/down related faults.
Memory tests
Cluster tests of non-JTAG components
Flash programming
In-system programming configuration
Pin-level diagnostics
On-going support

All of our tests are comprehensive, accurate, supported and reliable.

Call us today to get started.

Click here to learn more about onTAP Turnkey Service

JTAG.TECT Delivers onTAP to Russian Customers

admin — Mon, 09 Nov 2009 22:13:05 +0000

Flynn Systems – StarTest Technology Partnership Press Release

Flynn Systems and StarTest, along with their subsidiary JTAG.TECT (www.jtag-test.ru), have established a strategic relationship making JTAG.TECT the authorized Flynn Systems’ onTAP Boundary Scan Solutions dealer in Russia and countries of the former USSR. JTAG.TECT bundles onTAP Boundary Scan Solutions with their JTAG test solutions and services and provides complete JTAG tutorial and customer consulting, DFT and JTAG test program development support for onTAP. Flynn Systems has also integrated StarTest’s JTAG hardware and software environment with the JTAG test and programming tools of the onTAP Boundary Scan Series 4000.

Current and potential customers of onTAP Boundary Scan Solutions, and onTAP Series 4000 are able to use some of StarTest’s hardware and software solutions (DIMM/SODIMM External Modules, TAP Distributor and Bridge-For-Testability hardware tools, Operator Fault Spotlight software tool), as built-in features of the onTAP Boundary Scan Solution, usable throughout the users’ product lifecycle, including volume manufacturing and in-the-field troubleshooting and repair.

StarTest Ltd. (www.start-test.com) is a leading developer and supplier of JTAG test solutions in Israel across all hardware levels, including device, board, and system. StarTest is a team of test experts and engineers with more than 70 years of combined worldwide experience. StarTestserves as a JTAG and In-System Test (ICT) support supplier for:

Design-For-Testability (DFT) analysis and checking the DFT compliance of customer’s design before board layout and on all stages of the product lifecycle
JTAG (Boundary Scan) test program development, including on-board programming of CPLD, FPGA, flash, I²C, with different tools and platforms
ICT test program development for the Teradyne Z18xx testers with full test process support on the customer production facility

Flynn Systems Corp.(www.flynn.com) has provided test, debug, and programming solutions for the Boundary Scan test standard (JTAG IEEE 1149.1) for over ten years. Their onTAP software package delivers completely automated Boundary Scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-Boundary Scan devices interacting with the scan enabled devices. onTAP’s functionality also includes the capability to program flash devices using only the onTAP USB Test and Programming Cable. Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. Its satisfied customers include Intel, Qualcomm, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona. Flynn Systems’ onTAP provides Boundary Scan services for university research, avionics, defense systems, consumer goods, and medical electronics. It is based in New Hampshire with distributors and partners in Europe and in the Middle East.

onTAP BIST (Built In Self Test)

admin — Wed, 04 Nov 2009 16:47:13 +0000

Tests may be defined in script files which may then be translated into executable Serial Vector Format (SVF) files. The general approach is to place all of the required BSDL files into a folder and then to relate the BSDL files to circuit locations in declarations at the beginning of the script file. Once BIT_STRINGS are defined, instruction register scans may be created by simply declaring the instruction names to be used. And data scans can be created by concatenating BIT_STRINGS. String variables may be assigned values and then multiple variables may be concatenated. In addition literal string assignments may be used directly or mixed with variables.

Values are always expressed as binary strings, BIT_STRINGS. If zero and one values are present in a TDO string, the corresponding MASK bits will be set to one. If ‘X’ characters are present in a TDO string, the corresponding mask bits are set to zero.

The following example shows a very literal application of an IDCODE test to a three device chain. Comments, beginning with the ! character, explain the purpose of each statement and are consistent with SVF syntax. Note that onTAP allows C-like flow control expressions to be embedded within SVF files and that these expressions also use exclamation marks. onTAP distinguishes the two based on context.

As found in the onTAP folder on your computer:

Example of a User Defined IDCODE Test for Three Devices , U2,U3,U4( see onTAP/examples/UserDefinedTests/ idcode_batch.txt).

!Begin here….

create svf c:\bsdapps\UserDefined\idcode.svf; ! the following user statements will be placed in this SVF file

! onTAP uses the declarations between the begin chain and end chain lines to define the chain and to associate a BSDL file with each

! circuit location in the chain.

begin chain;

U2 = xc9536xl_pc44;

U3 = ispLSI2032VE;

U4 = 3032AL44;

end chain;

BIT_STRING u2_version, U2_part_num, U2_manuf_id, U2_required; // declare string variables for U2 IDCODE fields

BIT_STRING u3_version, U3_part_num, U3_manuf_id, U3_required; // declare string variables for U3 IDCODE fields

BIT_STRING u3_version, U3_part_num, U3_manuf_id, U3_required; // declare string variables for U4 IDCODE fields

BIT_STRING u4_version, U4_part_num, U4_manuf_id, U4_required; // declare string variables for U4 IDCODE fields

BIT_STRING zeroes;

state reset; ! place chain defined in TAPMAP in reset state

begin scan; ! onTAP creates one SIR scan in SVF file for U1,U2,U3

U2=IDCODE; ! if the BSDL file is in the folder, onTAP will find the opcode for U2’s IDCODE instruction

U3=IDCODE;

U4=IDCODE;

end scan;

! When compliled with Tools/Compose SVF, onTAP uses the declarations between begin scan and end scan lines

! to create an SIR scan that loads the IDCODE instructions.

U2_version = "XXXX"; ! IDCODE version field from U2’s BSDL file

U2_part_num = "1001011000000010"; ! part number

U2_manuf_id = "00001001001"; U2’s manufacturer’s id

U2_required = "1"; // required by BSDL spec

U3_version = "0001"; ! IDCODE version field from U3’s BSDL file

U3_part_num = "0000001100000001"; ! part number

U3_manuf_id = "00000100001"; U3’s manufacturer’s id

U3_required = "1"; // required by 1149.1 spec

U4_version = "0001"; ! IDCODE version field from U4’s BSDL file

U4_part_num = "0111000000110010"; ! part number

U4_manuf_id = "00001101110"; U4’s manufacturer’s id

U4_required = "1"; // required by BSDL spec

zeroes = "00000000000000000000000000000000"; // 32 zeroes

! TDI definesTest Data In and TDO defines Test Data Out.

! The strings in the TDO expression will be concatenated. LSB is on the right.

begin scan;

U2 = TDI(zeroes) TDO(U2_version+ U2_part_num+ U2_manuf_id+ U2_required); !concatenate BIT_STRINGS to form TDO string

U3 = TDI(zeroes) TDO(U3_version+ U3_part_num+ U3_manuf_id+ U3_required);

U4 = TDI(zeroes) TDO(U4_version+ U4_part_num+ U4_manuf_id+ U4_required);

end scan;

! When compiled with Tools/Compose SVF, the declarations between begin and end scan will be compiled into

! an SVF SDR scan.

! Examples of test statements that may be applied follow. onTAP will extract the measured value from SDR scans and will update

! BIT_STRING values so that they can be used in control flow branch expressions as shown below.

if ( U3_part_num != "0000001100000001" )

{

MESSAGE_PAUSE("U3’s IDCODE part number, %%s, is incorrect. Should be "0000001100000001"",U3_part_num);

}

if ( !(U2_part_num & "010"))

{

MESSAGE("bit 1 in U2’s part number reads low but should be high");

}

if ( U3_part_num != "0000001100000001" )

{

MESSAGE("U3’s part number reads %%s, but should read 0000001100000001", U3_part_num);

}

if ( FAIL )

{

MESSAGE("IDCODE test fails");

}

User defined script files may be compiled into SVF files by selecting the Compose SVF File menu item from the Tools menu.

When the command file, idcode_batch.txt, is called a new SVF file, IDCODE.SVF is created. Instructions such as “state reset;” are transferred directly into the new SVF file. onTAP compiles chain-wide SIR and SDR instructions based on a list of SIR and SDR instructions for each device in the target chain. SIR and SDR statements for the first device in a chain are listed first and statements for the last device are listed last.

A “log scan data on;” statement enables all scan-in and scan-out data to be captured in the scandata.txt file.

User Defined Instruction Statements

Statement	Use
create filename.svf;	Begin ceation of a new SVF file.
state state_name	Sequence TAP to designated state.
begin scan;	Begin steps that will be compiled into an SIR or SDR scan .
end scan;	End steps that will be compiled into an SIR or SDR scan .
BIT_STRING_name;	Declare string variables.
LogScanDataOn()	Enables logging of scan data to the project folder file scandata.txt.
LogScanDataOff()	Disables logging of scan data to the project folder file scandata.txt.