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Click here to learn more about our 30MHz Dual Channel JTAG Test and Programming cable and our Network License Manager.

Current build 4161. Updated March 4, 2010

MUST READ - IMPORTANT NOTE:
Currently we are developing support for industry standard USB JTAG cables such as the XILINX Platform USB and Altera USB Blaster.  In doing so, some routines within onTAP have been altered.  For the moment, some users may find that onTAP will not load because the Windows environment does not have the necessary settings to enable onTAP to properly function.  Please download this Microsoft® file – http://www.microsoft.com/downloads/details.aspx?familyid=9b2da534-3e03-4391-8a4d-074b9f2bc1bf&displaylang=en (if this link does not work, please copy and paste it into your browser).

"This [BLADE Network Research] is the second company I’ve used onTAP at, I’ve been using it for 3 or 4 years. Other vendors I’ve used tended to dismiss my problems or suggest a work around that just hides the problem. Lately I’ve been letting Flynn develop our applications because I just don’t have the time.  That’s another option if you need a boundary scan test but have way too many other testing details to sort out." F. Roberts ‘Test Engineer’ Blade Network Research

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Please click the "Download Now" button below to continue with the download.

Current build 4161. Updated March 4, 2010

IMPORTANT NOTE:
Currently we are developing support for industry standard USB JTAG cables such as the XILINX Platform USB and Altera USB Blaster.  In doing so, some routines within onTAP have been altered.  For the moment, some users may find that onTAP will not load because the Windows environment does not have the necessary settings to enable onTAP to properly function.  Please download this Microsoft® file – http://www.microsoft.com/downloads/details.aspx?familyid=9b2da534-3e03-4391-8a4d-074b9f2bc1bf&displaylang=en (if this link does not work, please copy and paste it into your browser).

VIEW INSTALLATION INSTRUCTIONS

Please click here to learn more about our Turnkey Boundary Scan Solutions

"This [BLADE Network Research] is the second company I’ve used onTAP at, I’ve been using it for 3 or 4 years. Other vendors I’ve used tended to dismiss my problems or suggest a work around that just hides the problem. Lately I’ve been letting Flynn develop our applications because I just don’t have the time.  That’s another option if you need a boundary scan test but have way too many other testing details to sort out." F. Roberts ‘Test Engineer’ Blade Network Research

Continue browsing

EVERYTHING YOU NEED

THE SMALL PRINT:

Keep an eye for some major upgrades to the software that are sure to greatly increase test capability, usability, and productivity.

Here’s to a successful and prosperous 2010!

Common tri-state control cells are groups of pins on a common net.  Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.

Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below. 

In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.

This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.

•  JTAG TAP infrastructure tests.
• Interconnect tests including detection of opens, shorts, stuck-at, bus-wire, pull-up/down related faults.
• Memory tests
• Cluster tests of non-JTAG components
• Flash programming
• In-system programming configuration
• Pin-level diagnostics
• On-going support

Click here to learn more about onTAP Turnkey Service

• Design-For-Testability (DFT) analysis and checking the DFT compliance of customer’s design before board layout and on all stages of the product lifecycle
• JTAG (Boundary Scan) test program development, including on-board programming of CPLD, FPGA, flash, I²C, with different tools and platforms
• ICT test program development for the Teradyne Z18xx testers with full test process support on the customer production facility

How onTAP Detects and Diagnoses Mid-State Shorts

Mid-state shorts are bridging faults that result in a mid-state voltage level rather than a hard low or high level. In our experience at Flynn Systems when working with customers, we have found the condition occurs where short circuits exist:

1. between some boundary-scan pins on FPGA devices when only one boundary scan pin is present on a PCB net
2. across pins on resistor networks where the resistors lie between the shorts fault and scannable pins, and again on nets that have only one boundary-scan pin

Mid-state shorts, like any bridging fault, can result in system level applications failures if not detected and cleared. The difficulty is that these shorts will not be detected by traditional boundary scan shorts detection algorithms where zero or one logic levels must be detected. The reason is that at the capture cell on single-pin nets, the capture value is equal to the value being actively driven from the same pin.

In the case of the resistor network, it is easy to see how the resistors can isolate the capture value from the value measured at the physical short. In the case of the FPGA pins the reasons are not quite so clear, but apparently sufficient impedance exists between the bidirectional cells and physical pins so that the input cell sees the value driven from the drive cell, not the value measured at the physical short. Again, the capture value is equal to the expected value, producing a PASS.

How can Mid-State Shorts be Detected?

As might be expected, MID-STATE shorts can be detected by a test pattern that uses tri-state, high impedance values, Z, in combination with zero and one values. One difficulty, however, is that since Z is a passive condition, this approach is likely to result in unpredictable numbers of false failures. Another problem is that the number of potential test scans required can be quite large.

onTAP addresses these difficulties in several ways. First, to achieve a manageable number of test patterns, standard Wagner test popular in boundary scan testing and known for their compactness and effectiveness, are employed. But instead of using only 0-1 test patterns, 0-Z and 1-Z patterns are also used. This is effective and will detect the shorts, but will inevitably also produce false failures.
To deal with the false failures, onTAP actively interrogates all indicted net combinations at run time with a more exhaustive
0-1-Z pattern that eliminates false failures but indicts any MID-STATE shorts
conditions.
 

Procedure for Running Tests in Parallel

Create a separate folder for each board to be tested and in the folder place all of the tests that will be run for a board.

Launch an ontap_parallel.exe for each board to be tested, and for each instance of ontap_parallel.
exe, browse to a folder with the tests for a designated board. In the SVF Files list, check the SVF files that will be run for the board.

Return to the first instance of ontap_parallel.exe and check the boards that you wish to run in the Board list.

Click Run Checked Board Folders to run the tests for one or more folders. Test results are left in the .test and .fail files for each test in each folder. The test and diagnostic messages can be seen on the screen by selecting, as opposed to checking, a board and then selecting an SVF file.