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	<title>Flynn Systems</title>
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	<link>http://www.flynn.com</link>
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	<lastBuildDate>Thu, 02 Feb 2012 20:19:53 +0000</lastBuildDate>
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		<title>onTAP Download Request</title>
		<link>http://www.flynn.com/messages/ontap-thank-you/</link>
		<comments>http://www.flynn.com/messages/ontap-thank-you/#comments</comments>
		<pubDate>Wed, 03 Aug 2011 14:00:04 +0000</pubDate>
		<dc:creator>Update</dc:creator>
				<category><![CDATA[Messages]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=2006</guid>
		<description><![CDATA[Updates Thank you for your continued interest in onTAP Series 4000 with support for IEEE 1149.1 and IEEE 1149.6; and, introducing ShowMe! A whole new way to look at cluster test debugging. All onTAP users with active software maintenance and 30-day evaluation licenses may download updates.&#160; If your support contract is expired, please do not [...]]]></description>
			<content:encoded><![CDATA[<p><strong><big>Updates<font size="2"> </font></big></strong><font size="2"> </font></p>
<p><font size="2"><span style="font-size: medium;"><strong>Thank you for your continued interest in onTAP Series 4000 with support for IEEE 1149.1 and IEEE 1149.6; </strong><strong>and, introducing ShowMe! A whole new way to look at cluster test debugging.</strong></span><strong><font size="2"> <br />
</font></strong></font></p>
<p><font size="2"> </font></p>
<ul><font size="2"></p>
<ul>
<li><strong>All onTAP users with active software maintenance and 30-day evaluation licenses may download updates.&nbsp;</strong></li>
<li><span style="color: rgb(255, 0, 0);"><strong>If your support contract is expired, please do not download the latest version of onTAP.</strong></span></li>
<li>Updates are cumulative &ndash; we strongly advise keeping up with the latest builds.</li>
<li>For a complete listing of all software changes look in the onTAP online HELP section, &quot;onTAP Change History.&quot;</li>
<li>Please fill in the required information below to receive your updated version of onTAP.</li>
</ul>
<p>    </font></ul>
<p><font size="2"> </font></p>
<p><strong>Current build 4300. Updated January 11, 2012</strong><br />
    Please click the button below to continue with the download.</p>
<p><a href="http://flynn.com/files/downloads/ontap_setup.exe"><img height="24" width="127" alt="Download onTAP Boundary Scan Software, begin testing today!" src="/wp-content/uploads/image/PICS/download.gif" /></a></p>
<p><font size="2"> </font></p>
<p><b>&quot;This [BLADE&nbsp;Network&nbsp;Research] is the second company I&rsquo;ve used onTAP  at, I&rsquo;ve been using it for 3 or 4 years. Other vendors I&rsquo;ve used tended  to dismiss my problems or suggest a work around that just hides the  problem. Lately I&rsquo;ve been letting Flynn develop our applications because  I just don&rsquo;t have the time.&nbsp; That&rsquo;s another option if you need a  boundary scan test but have way too many other testing details to sort  out.&quot; F. Roberts &#8216;Test Engineer&#8217; Blade Network Research<br />
    </b></p>
<p><a href="http://www.flynn.com/boundary-scan-products-and-services/highspeed-jtag-test-and-programing-cable/"><strong>Click here to learn more about our 30MHz Dual Channel JTAG&nbsp;Test and Programming cable.</strong></a></p>
<p><span style="font-size: larger;"><strong>Now Supporting IEEE 1149.6 &amp; Introducing <em>ShowMe! </em>A whole new way to look at cluster test debugging.</strong><b><i><br />
    </i></b></span></p>
<p><a href="http://flynn.com">Continue browsing</a></p>
<table cellspacing="1" cellpadding="1" border="1" style="width: 585px; height: 333px;">
<tbody>
<tr>
            </tr>
<tr>
<td bgcolor="#000099" width="95" colspan="2" style="text-align: center;"><span style="font-size: small;"><strong><span style=""><span style="color: rgb(255, 255, 255);">onTAP Build </span></span></strong></span><span style="font-size: small;"><strong><span style=""><span style="color: rgb(255, 255, 255);">Change Log </span></span></strong></span></td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4300</strong></span></span></td>
<td>
<ul>
<li>Added capability to view Flash verify results using access from Flash Settings Control Panel.</li>
<li>Added new capability to Flash Control Panel for start and end flash programming address settings.</li>
<li>Adjusted dimensions on Test screen</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4299</strong></span></span></td>
<td>
<ul>
<li>Corrects problem in MID-STATE shorts test where some resistive shorts faults were not detected.</li>
<li>Corrects problem with Wait Cursor not terminating on TestGen page.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4296</strong></span></span></td>
<td>Adds capability for user to change I2C device address on Flash Settings control panel.</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4294</strong></span></span></td>
<td>
<ul>
<li>Upgrades FLASH Control Panel to include an optional number of TCK clocks between programming addresses, allowing more time for programming operations.</li>
<li>Upgrades IEEE 1149.6 AC testing so that jumpers are not required across capacitors. Capacitors in the test should be matched to onTAP&rsquo;s CAPACITOR model on the Non Scan page.&nbsp; Loopback connections are best handled using a ProjectPinMap.txt model of a connectors pin-to-pin connections. The ProjectPinMaps file is located in a user&rsquo;s project folder.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4291</strong></span></span></td>
<td><span style="font-size: small;">Introduces a User&rsquo;s Control Panel for run-time FLASH programming and verifying settings. The Control Panel is accessible from the Test screen and the Test menu.</span></td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4290</strong></span></span></td>
<td>
<ul>
<li>Upgrades <i>PlayRecord</i> feature for flash programming.</li>
<li>Upgrades ability to assign net names to pin in <i>Compose Netlist</i> tool.</li>
<li>Upgrades handling of binary flash data files.</li>
<li>Upgrades DLLs.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4289</strong></span></span></td>
<td>
<div>Speeds up scrolling and test program execution in ProScan.</div>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4288</strong></span></span></td>
<td>
<ul>
<li>Provides capability to access EXTENDED_ADDRESS, SEGMENT_ADDRESS and low word address, LOW_ADDRESS, from within DTS programming and verify models. Previously this information was available only within the FILE_ADDRESS variable.</li>
<li>Enhances capability using the <i>Compose Netlist</i> tool to build netlists based on BSDL files and the Auto JTAG Chain Detect tool.</li>
<li>Corrects DTS DISABLE section for GenRad ICT chain applications.</li>
<li>Makes adjustments for Chinese language screen presentations.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4287</strong></span></span></td>
<td>
<ul>
<li>Corrects parsing restrictions when translating User Defined Script files with the <strong>Compose SVF</strong> file tool.</li>
<li>Ensures that<strong> INSTRUCTION CAPTURE </strong>tests are not implemented for any instruction loading scans if &ldquo;tap instruction capture&rdquo; is not selected on the <strong>TestGen</strong> page</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4285</strong></span></span></td>
<td><strong>Cuts NAND&nbsp;FLASH programming time at least 3X!</strong></td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4283</strong></span></span></td>
<td>
<ul>
<li>Modifies and improves test generation related to assigned logic elements.</li>
<li>Includes Net Order list, used to show sequence of net names in ProScan, in Copy Settings operation.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4281</strong></span></span></td>
<td>General update for improved test reporting.</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4279</strong></span></span></td>
<td><span style="font-size: small;">Upgrades and corrects cluster test operation in multiple JTAG chain environments.</span></td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4278</strong></span></span></td>
<td>
<div style="margin-right:1.5pt;<br />
                text-indent:-.25in;"><span style="font-size: small;"><span style="line-height: 115%;">&middot;<span style="font: 7pt &quot;Times New Roman&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span><span style="line-height: 115%;">Upgrade for operation with onTAP Network License Manager.</span></span></div>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4276</strong></span></span></td>
<td>
<ul>
<li>Corrects problem presenting all diagnostic messages for TAP test failures.</li>
<li>Adjusts synchronization with onTAP Network License Manager server .</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4274</strong></span></span></td>
<td>
<ul>
<li>Speeds up reloading test projects on the Development screen.</li>
<li>Improves management of changes to the jumpers list.</li>
<li>Upgrades auto detection of JTAG chains. Results are placed in a file as well as shown on the Test screen</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4273</strong></span></span></td>
<td>
<div>Removes restriction against use of period characters in path name to project folders, although including period characters in pathnames is not recommended.</div>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4272</strong></span></span></td>
<td>
<ul>
<li><span>&nbsp;</span>Adds capability to place related differential pair nets together in test report and on ProScan screen.</li>
<li>Upgrades ability to add alternate IDCODES. See Test menu.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4271</strong></span></span></td>
<td>
<ul>
<li>Adds capability to diagnose only opens faults and filter out other faults for a/c coupled differential pins. See Diagnose Only Opens on Development screen&rsquo;s Settings page.</li>
<li>Upgrades .test file, accessed using View Test Report button on Test screen. Test values are truncated at the point where a test file stops in the events that the fault count exceeds MAX FAILS.&nbsp; ProScan screens have been upgraded in a similar manner.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4270</strong></span></span></td>
<td><span style="font-size: small;">Upgrades diagnostic processing</span></td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4269</strong></span></span></td>
<td>
<ul>
<li>Adds search control on Non-Scan page to search for model names.<span><br />
                    </span></li>
<li>Adds capability to test only differential circuits while disabling other test activity.<span><br />
                    </span></li>
<li>Upgrades diagnostic resolution for circuits having intermittent test results.</li>
<li>Corrects potential program exception problem when jumpers are added.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build 4266</strong></span></span></td>
<td><span style="font-size: small;">Adds a tool to the Cables menu that facilitates updating a project&rsquo;s adaptor files when an onTAP USB Dual Port cable is replaced</span><br />
                <img height="88" width="302" src="http://www.flynn.com/wp-content/uploads/image/PICS/New%20Cable%20Menu%20Add%20Cable.png" alt="Image showing new onTAP JTAG CABLE menu" /><br />
                &nbsp;</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build&nbsp;</strong></span><strong><span style="font-family: Arial;">4265</span></strong></span></td>
<td>
<p>&nbsp;</p>
<ul>
<li>Corrects problem displaying DTS lines in ShowMe! debug tool.</li>
<li>Corrects crash condition that could occur when maximizing and minimizing screens in a particular sequence.</li>
<li>Provides additional updates for TestGen page settings and procedures.</li>
<li>Corrects problem showing negative numbers in reports files for nets not having scan pins.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build&nbsp;</strong></span><strong><span style="font-family: Arial;">4260</span></strong></span></td>
<td>
<ul>
<li>Corrects problem restoring HIGHZ test procedure name when reloading a test on the TestGen page.</li>
<li>Corrects problem running large test suites on the MFG Test screen.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build&nbsp;</strong></span><strong><span style="font-family: Arial;">4259</span></strong></span></td>
<td>
<ul>
<li>Updates onTAP so that IEEE 1149.6 A/C tests work with multiple JTAG chains and onTAP USB cables.</li>
<li>Corrects problem restoring Clamp instruction when reloading a test on Development screen.</li>
<li>Upgrades user test messages on Test screen.</li>
<li>Corrects test generation handling cells where the control cell is the same as the drive cell.</li>
<li>Corrects problem in cluster tests when using OL and OH instructions&nbsp; on external pins that are not in a pin group.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build&nbsp;</strong></span><strong><span style="font-family: Arial;">4257</span></strong></span></td>
<td>
<ul>
<li>Adjusts TCK rate adjustments in the Test and Programming Cable dialogue.</li>
<li>Adjusts for IEEE 1149.6 operations when testing across multiple JTAG chains</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build&nbsp;</strong></span><strong><span style="font-family: Arial;">4256</span></strong></span></td>
<td>
<ul>
<li>Improves test generation and management of bus signals when bidirectional pins share a common tri-state control cell.</li>
<li>Adds capability to set more guards using the Guards+Attributes tab within ProScan.</li>
<li>Shows all pins on Jumpers page. Previously, only devices having more than four pins were shown in the FromPin and ToPin lists.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span class="Apple-style-span" style="font-size: medium;"><span style="font-family: Arial;"><strong>Build&nbsp;</strong></span><strong><span style="font-family: Arial;">4253</span></strong></span></td>
<td><span style="font-size: small;">Shows header package pin assignments for Cluster tests on the Cluster page</span>.</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4251</span></strong></span></p>
</td>
<td>
<ul>
<li><span style="">Adds additional Debug menu items including the ability to learn measured test results and to disable tests at individual test vectors during debug </span></li>
<li><span style="">Upgrades capability in ProScan to examine ATG results for individual pins and to produce individual test scans to check the ATG results. This is intended to help debug test activity in complex non-scan circuits.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4250</span></strong></span></p>
</td>
<td><span style="font-size: small;">Adjusted some screen layouts including positions of controls.<br />
                </span></td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4249</span></strong></span></p>
</td>
<td>
<ul>
<li><span style="">Ensures that all pins are properly updated in cluster test applications having multiple chains where pin instructions related to more than one chain are used in the same scan.</span></li>
<li><span style="">Corrects Manufacturing&nbsp; screen layout problem with Cable Test group control box.</span></li>
<li><span style="">Upgrades GUARD STRING editor allowing guards to be set on a per vector basis as well as on a per pin basis.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4248</span></strong></span></p>
</td>
<td>
<ul>
<li><span style="">Upgrades test reports, fault coverage reporting format, and tool to summarize fault coverage reports. See onTAP Reports menu.</span></li>
<li><span style="">Adds tool to automatically create a loopback list for connectors, helpful when logic devices separate connector pins from access to scan pins. See &ldquo;loopback&rdquo; in on line Help.</span></li>
<li><span style="">Adds DTS Library models and makes them accessible from Cluster page.</span></li>
<li><span style="">Adds flash programming models for S29AL032 as well as several logic models.</span></li>
<li><span style="">Improves fault coverage in environments with many logic devices, buffers, and transceivers between scan pins.</span></li>
<li><span style="">Corrects potential problem related to&nbsp; EXTERNAL pin declarations in DTS models.</span></li>
<li><span style="">Corrects problem reliably showing scan pin assignments and target device pin matchups on Cluster page.</span></li>
<li><span style="">Corrects problem with memory leak affecting some applications.</span></li>
<li><span style="">Updates DLLs.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4247</span></strong></span></p>
</td>
<td>
<ul>
<li><span style="">Introduces a new capability to reduce flash programming times by recording programming overhead and flash data in a binary record file. See &ldquo;PlayRecordBinary&rdquo; in the DTS Test Program Format document within onTAP Help.</span></li>
<li><span style="">Reduces test execution time within the ProScan environment.</span></li>
<li><span style="">Adds capabillity on the TestGen Development page to more clearly change cluster test modes of JTAG devices to Extest, Bypass, or Highz.</span></li>
<li><span style="">Eliminates requirement to use the DisablePreprocessBuffers instruction when using PlayRecordOn/Off instructions in flash programming models.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4246</span></strong></span></p>
</td>
<td><span style="font-size: small;"></p>
<ul>
<li><span style="">Adds default to place unused scan devices in HIGHZ mode vs BYPASS mode. </span></li>
<li>Corrects problem reading DTS models from the commands list in ProScan.</li>
<li>Upgrades and corrects the ShowMe! debugger.</li>
</ul>
<p>                </span></td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4245</span></strong></span></p>
</td>
<td><span style="font-size: small;">Corrects problem when assigning &ldquo;No Test&rdquo; to JTAG Chains in cluster test applications<br />
                </span></td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4244</span></strong></span></p>
</td>
<td>
<ul>
<li><span style="font-size: small;">Adds debug capability to ProScan screen. See discussion related to debugging and setting guards in the help for the ProScan screen.</span></li>
<li><span style="font-size: small;">  Generalizes translation capabilities for CadSoft Eagle style netlists.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4243</span></strong></span></p>
</td>
<td>
<div style="margin-right: 1.5pt;"><span style="">Upgrades ProScan screen: synchronizes presentations in splitter windows during single-stepping; enables Auto Detect button; corrects potential crash condition.</span></div>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4242</span></strong></span></p>
</td>
<td>
<div style="margin-right: 1.5pt;"><span style="">Upgrades PADS POWER_PCB netlist translator to extract part information from *MISC* section.</span></div>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4241</span></strong></span></p>
</td>
<td>
<div style="margin-right: 1.5pt;"><span style="">Corrects problem retaining new guards settings.</span></div>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4240</span></strong></span></p>
</td>
<td>
<ul>
<li><span style="font-size: small;">Ensures that a clock is developed for memory cluster tests where the clock pins are differential pairs declared in the BSDL file.</span></li>
<li><span style="font-size: small;">Corrects problem with settings for dual channel high speed onTAP USB cable so that full range of TCK rates is available.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95">
<p><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4239</span></strong></span></p>
</td>
<td>
<ul>
<li><span style="font-size: small;">Adds capability to include test setup messages, shown when loading or selecting an SVF file, with each SVF. To use, select an SVF file from list on Test screen and click the Test Setups / User Messages button.</span></li>
<li><span style="font-size: small;">Loads SVF file when accessing Test screen following test generation on the Development screen.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span style="font-size: medium;"><span style="font-family: Arial;"><strong>Build </strong></span><strong><span style="font-family: Arial;">4238</span></strong></span></td>
<td>
<p class="MsoPlainText" style="margin: 0in 0in 0pt;"><span style="font-size: small;"><span><span style="font-family: Arial;">Changes centered around settings on TestGen page plus various program corrections and upgrades.</span></span></span></p>
</td>
</tr>
<tr>
<td width="95"><span style="font-size: small;"><span><span><span><big><strong>Build 4235</strong></big></span></span></span></span></td>
<td><span style="font-size: small;">Adds provisions to allow running single-chain applications using onTAP USB cables when the serial number of the USB cable in the related adaptor file does not match the S/N of the cable in use.&nbsp; This condition previously&nbsp; required a user to&nbsp; reload an SVF file</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4234</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Corrects possible crash condition when looping tests or running burn-in<br />
                    </span></li>
<li><span style="font-size: small;">Allows jumpers to be added for no-connect pins<br />
                    </span></li>
<li><span style="font-size: small;">Upgrades syntax check on Guards page<br />
                    </span></li>
<li><span style="font-size: small;">Adds syntax check to ensure that declared subroutines have a body<br />
                    </span></li>
<li><span style="font-size: small;">Corrects potential crash when selecting Save Project from the File menu<br />
                    </span></li>
<li><span style="font-size: small;">Corrects problem using hex notation X&rsquo; when passing constant values as arguments to subroutines</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><span style="font-size: small;"><big><strong>Build 4233</strong></big></span></td>
<td>
<ul>
<li><span style="font-size: small;">Upgrades handling of Jumpers so that jumper settings are implemented directly in a netlist when an application netlist is read by onTAP<br />
                    </span></li>
<li><span style="font-size: small;">Corrects test generation problem involving logic element circuits<br />
                    </span></li>
<li><span style="font-size: small;">Improves management of onTAP USB cable in test start-up situations, when a UUT&rsquo;s power is cycled, and when a USB cable is disconnected / reconnected<br />
                    </span></li>
<li><span style="font-size: small;">Upgrades Development screen&rsquo;s TestGen page so that test procedures may be refined by selecting specific TAP instructions or procedures. Test generation will proceed normally without changing any of the check box selections on the TestGen page.<br />
                    </span></li>
<li><span style="font-size: small;">Reduces clutter on the Settings page. Moves Adaptor file settings to the Cables menu pages from the Settings page. An onTAP USB cable-based adaptor file is created by default if an adaptor file doesn&rsquo;t exist<br />
                    </span></li>
<li><span style="font-size: small;">Adds project notes access on the Projects page, enabling users to maintain notes about aspects of a project<br />
                    </span></li>
<li><span style="font-size: small;">Upgrades handling of GetKeyboardStr instruction to support the Cancel button so that Cancel results in a null string length</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4230</strong></big></td>
<td>
<ul>
<li>Drops need to have Microsoft .NET Framework installed when running onTAP. This was requirement had begun with build 4229.</li>
<li>Corrects problem that required program reloads when cycling power on boards having more than one JTAG chain.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4227</strong></big></td>
<td><span style="font-size: small;">Adds capability to refine ShowMe! capture data for cluster test debug purposes.<br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4226</strong></big></td>
<td><span style="font-size: small;">Includes adjustment for Parallel test option when using onTAP Network License Manager</span>.</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4225</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Introduces <i>ShowMe!</i>, a new tool for debugging cluster tests. <i>ShowMe!</i> Is accessible from the Debug menu and provides a spreadsheet-like view of drive and capture values at all pin groups, pins, and DTS program variables throughout a test. <i>ShowMe! </i>can be run with or without a test/program cable attached.</span></li>
<li><span style="font-size: small;">Allows the debug mode &lsquo;Log TDO HEX Data&rsquo; to run and capture data with or without a test/program cable present.<br />
                    </span></li>
<li><span style="font-size: small;">Makes default status of JTAG devices &lsquo;unsafe&rsquo; in Test Only Safe Circuit mode, unless the JTAG device&rsquo;s reference designator is placed in the &hellip;project_settings\safe_devices_&lt;test_name&gt;.txt list<br />
                    </span></li>
<li><span style="font-size: small;">Simplifies and improves controls on USB Cables dialog used to create adaptor files for USB cables.<br />
                    </span></li>
<li><span style="font-size: small;">Updates Browse control on Projects page</span></li>
<li><span style="font-size: small;">Adds text to scandata debug file showing failing pin names</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4221</strong></big></td>
<td><span style="font-size: small;">Ensures that BYPASS and not HIGHZ instructions are used in cluster tests</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4220</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Add netlist translator support for Zuken CFF files</span></li>
<li><span style="font-size: small;">Adds safeguard when testing nets having JTAG pins and the associated JTAGdevice is in Bypass mode.&nbsp; These nets will not be tested by other JTAG pins on the nets unless the JTAG device in Bypass is listed in the safe_circuits_&lt;test_name&gt;.txt file</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4219</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Updates settings and presentation of scan pin assignments on the Cluster page</span></li>
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<p>                <![endif]--><span style="font-family: 'Arial','sans-serif';">Adds new tests to quickly check the onTAP USB cable from the test screens and USB Cable settings page</span></span></li>
</ul>
</td>
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<tr>
<td width="95"><big><strong>Build 4218</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds a Settings change log with an undo capability on the ProScan screen when using the Guards+Attibutes page. This provides a convenient way to make guards and attribute changes, compile, test, review results, and undo changes as required</span></li>
<li><span style="font-size: small;">Adds additional diagnostic information related to TAP test failures. Detailed bit information for instruction capture and IDCODE code responses is provided in diagnostic messages</span></li>
</ul>
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<tr>
<td width="95"><big><strong>Build 4217</strong></big></td>
<td>
<p><span style="font-size: small;">Adjusts ProScan so that screen is updated only once after a recompile.<br />
                </span></p>
<p><span style="font-size: small;">Includes Microsoft Visual Studio redistributable DLLs in installation package so that onTAP should run without the MS redistributable. However, if there are DLL complaints when loading onTAP, please run the MS redistributable at this link<br />
                </span><span style="font-size: 11pt;"><a href="http://www.microsoft.com/downloads/en/details.aspx?familyid=A7B7A05E-6DE6-4D3A-A423-37BF0912DB84&amp;displaylang=en"><span style="font-size: small;">http://www.microsoft.com/download/en/details.aspx?familyid=A7B7A05E-6DE6-4D3A-A423-37BF0912DB84&amp;displaylang=en</span></a></span></p>
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<tr>
<td width="95"><big><strong>Build 4211</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Upgrades &ldquo;Update Other Adaptors&rsquo; tool&nbsp; on USB Cables dialogue, allowing all adaptor files to be updated with USB port and TCK rate assignments.<span style="font-family: 'Arial','sans-serif';"><br />
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<p>                <![endif]--></span></li>
<li><span style="font-size: small;">Adds &lsquo;drag-and-drop&rsquo; capability to reorder SVF files in SVF Files list on Manufacturing Test screen</span><span style="font-size: 11pt;">.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4210</strong></big></td>
<td><span style="font-size: small;">Ensures correct use of Interconnect,Bypass and Interconnect,Bypass(NO-HIGHZ) instructions on TestGen page</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4209</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Upgrades GenRad ICT translator<br />
                    </span></li>
<li><span style="font-size: small;">Adds Direct Drive, allowing programming of serial flash directly from USB cable leads, bypassing boundary scan<br />
                    </span></li>
<li><span style="font-size: small;">Upgrades handling of alternate IDCODES at run-time<br />
                    </span></li>
<li><span style="font-size: small;">Updates onTAP DLLs</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4206</strong></big></td>
<td><span style="font-size: small;">Updates run-time support for DTS models</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4205</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds capability to accept alternate IDCODES for JTAG devices at run-time. Press F1 for Help on Test screen for details<br />
                    </span></li>
<li><span style="font-size: small;">Corrects problem where integer array expressions can be excluded in SVF files</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4204</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Corrects diagnostic messages for %PIN: expressions for DTS models that use pin groups where individual pins are declared as EXTERNAL</span></li>
<li><span style="font-size: small;">Corrects screen text for Windows UI fonts and resolutions where text on the screen can be cropped</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4203</strong></big></td>
<td><span style="font-size: small;">Fixes program exception related to running cluster tests with multiple JTAG chains</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4200</strong></big></td>
<td><span style="font-size: small;">Improves asserting guards during cluster tests<br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4198</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds capability to directly run binary flash files. ( Check with technical support to see which flash devices have been tested.)</span></li>
<li><span style="font-size: small;">Reduces test execution times<br />
                    </span></li>
<li><span style="font-size: small;">Adds preventive code for potential program exceptions<br />
                    </span></li>
<li><span style="font-size: small;">Upgrades Netlist Merge tool providing capability for accepting user-edited merge_pins files. Adds debug trace file that shows sequence of merge steps<br />
                    </span></li>
<li><span style="font-size: small;">Adjusts screen settings for PCs in China</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4194</strong></big></td>
<td><span style="font-size: small;">Upgrades code related to serial flash programming models</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4193</strong></big></td>
<td><span style="font-size: small;">Corrects problem in DTS models when passing in values to subroutines and calling subroutines from subroutines<br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4192</strong></big></td>
<td>Usability enhancements</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4191</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds capability to write message strings with variables from within the ShowFail(message) instruction <br />
                    </span></li>
<li><span style="font-size: small;">Adds capability to run script-generated SVF files with updated scans based on varying bit string values</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4190</strong></big></td>
<td><span style="font-size: small;">Corrects problem updating pin register values in DTS models when running cluster tests in multi-chain applications</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4189</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Corrects problem setting preload values for 1149.6 AC differential receivers when the pin type is bidirectional<br />
                    </span></li>
<li><span style="font-size: small;">Corrects problem setting guards from ProScan on bidirectional differential receiver pins. </span></li>
<li><span style="font-size: small;">Corrects problem related to option on Jumpers page to automatically add jumpers for IEEE 1149.6 testing of capacitively coupled devices. Extends capability so that in-line resistors are accounted for</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4187</strong></big></td>
<td><span style="font-size: small;">Upgrades User Defined script capabilities </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4186</strong></big></td>
<td><span style="font-size: small;">Adds capability to run Play/Record binary files in buffered mode, reducing run time and eliminating program latency while in the Run-Test/Idle state</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4184</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Updates support for onTAP GPIO Serializer<br />
                    </span></li>
<li><span style="font-size: small;">Corrects test generation problem when pins from devices in multiple JTAG chains are used in cluster tests<span style="font: 7pt 'Times New Roman';"><br />
                    </span></span></li>
<li><span style="font-size: small;">Upgrades handling of unplug-plug events for onTAP USB cables</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4183</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds support for AUG netlist format.<span style="font: 7pt 'Times New Roman';"><br />
                    </span></span></li>
<li><span style="font-size: small;">Corrects problem showing bit-string message values in user-defined scripts. </span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4181</strong></big></td>
<td><span style="font-size: small;">Updates User Defined code. </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4179</strong></big></td>
<td><span style="font-size: small;">Ensures that pins are alternately selected to drive a net when the pins are joined by low-ohm resistors, providing each pin a chance to drive high and low multiple times.</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4178</strong></big></td>
<td><span style="font-size: small;">Allows for use of for-loops in User Defined tests.</span><span style="font-size: 11pt;"> <br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4177</strong></big></td>
<td><span style="font-size: small;"><span>Updates Protel netlist translator</span></span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4174</strong></big></td>
<td><span style="font-size: small;"><span>Sets preload capture values for to opposite value of expected capture values.</span></span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4173</strong></big></td>
<td><span style="font-size: small;">Updates 1149.6 related settings. </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4172</strong></big></td>
<td><span style="font-size: small;">Add preload provisions for 1149.6 sample instruction. </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4171</strong></big></td>
<td><span style="font-size: small;">Corrects problem related to incorrect test values in multi-chain applications for the vectors following the SAMPLE instruction for some configurations. </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4170</strong></big></td>
<td>Improves usability of ProScan graphical debug environment by adding advanced controls for search, pin level diagnostics, and ease of switching between and running tests.</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4166</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Improves Reset operation of USB cable when Reset buttons are clicked and when calling Reset from the onTAP DLLs.</span></li>
<li><span style="font-size: small;">Adjusts diagnostic message for no-connect pins in the event of stuck-at faults.</span></li>
<li><span style="font-size: small;">Upgrades use of&nbsp; EXTEST_TRAIN instruction for 1149.6 AC testing.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4165</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds pin-wiggle capability in ProScan for 1149.6 AC coupled pins.<br />
                    </span></li>
<li><span style="font-size: small;">Upgrades Guards+Attributes tab in ProScan to facilitate setting guards, attributes, recompiling, and rerunning tests from within ProScan.<br />
                    </span></li>
<li><span style="font-size: small;">Corrects problem showing test messages for multi-chain applications.<br />
                    </span></li>
<li><span style="font-size: small;">Adjusts FabMaster netlist translator code.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4164</strong></big></td>
<td><span style="font-size: small;">Corrects DTS test generation where EXTERNAL pin declarations are used when large numbers of cells with common control cells are present</span>.</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4163</strong></big></td>
<td><span style="font-size: small;">Adds screen to view onTAP Network License Manager&rsquo;s server screen.<br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4162</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Updates for Play/Record feature used when loading configuration files.<br />
                    </span></li>
<li><span style="font-size: small;">Updates for licensing and onTAP Network License Manager. </span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4161</strong></big></td>
<td><span style="font-size: small;">Corrects problem with IDCODE tests resulting from millisecond delay settings in multi-chain tests or when specified on the Settings page. <br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4160</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Includes updates for programming Lattice FPGAs.<br />
                    </span></li>
<li><span style="font-size: small;">Upgrades differential pair testing. Reads port groupings of differential pair pins in BSDL files and accounts for all positive and negative side pins using BSDL files and netlist.</span><span style="font-size: 11pt;"> </span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4158</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds Play/Record feature for SVF program configuration files. Play/Record converts SVF files to binary, allowing faster programming. Play / Record can be enabled from the Cables menu for specific SVF files. <br />
                    </span></li>
<li><span style="font-size: small;">Ensures that guard constraints in the Browse Circuit view are updated when a guard condition is changed the Vector view</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4157</strong></big></td>
<td>Improves stability in ProScan debugging environment</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4156</strong></big></td>
<td><span style="font-size: small;">Enables manual input of text in the License Request Folder Edit box &nbsp;on the Help About page</span>.</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4155</strong></big></td>
<td><span style="font-size: small;">Statically links Windows DLLs to enable that user&rsquo;s have the correct DLLs</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4153</strong></big></td>
<td>
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<p><!--{12653821309034}--><span style="font-size: small;"><span style="font-family: 'Arial','sans-serif';">Corrects potential false failures in multi-chain applications</span></span>                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                </meta><br />
                </meta><br />
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                </td>
</tr>
<tr>
<td width="95"><big><strong>Build 4152</strong></big></td>
<td><span style="font-size: small;">Ads stability when generating tests for some multi-JTAG chain applications</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4151</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Corrects problem writing failure reports from Mfg test screen when Operator, Serial Number, and Unit Type text strings are entered. </span></li>
<li><span style="font-size: small;">Adds pin-wiggling capability on Nets screen and ProScan for the Xilinx USB cable</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4150</strong></big></td>
<td>Adds code for Xilinx USB Platform Cable support (<strong>Beta</strong>).</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4149</strong></big></td>
<td><span style="font-size: small;">Adds SAMPLE/PRELOAD instruction as a default in first cluster test scan prior to EXTEST instruction.</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4148</strong></big></td>
<td>
<ul>
<li><span style="font-size: 11pt;">Corrects test generation for circuits with shared control cells to ensure that only one driver on a net is active at one time.</span><span style="font-size: 11pt;"><br />
                    </span></li>
<li><span style="font-size: 11pt;">Moves license file, LogicPinMaps and other files within the onTAP folder to the c:\Flynn Systems Corp\onTAP folder, in order to avoid write protected folders within the c:\Program Files folder. The default installation folder is still c:\Program Files\onTAP.</span></li>
<li><span style="font-size: 11pt;">Adds code in preparation of support for the Xilinx USB Cable II.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4146</strong></big></td>
<td><span style="font-size: small;">Improves coverage for handling guards when current limiting is enabled<br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4145</strong></big></td>
<td>
<ul>
<li>Corrects problem with current-limiting option.<span><br />
                    </span></li>
<li>Corrects problem writing serial-number-specific files when testing from the Manufacturing Test screen.</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4143</strong></big></td>
<td>
<ul>
<li>Adds netlist translator support for IPL&nbsp;Wirelist netlists</li>
<li>Includes adjustment for the current limiting option</li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4142</strong></big></td>
<td><span style="font-size: small;">Changes the Scan switch factor on the Settings page to a current limiting switch factor (CLSF). Values greater than one limit the total number of pins that can be active at one time during the opens, stuck-at, and pull resistor tests.</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4141</strong></big></td>
<td><span style="font-size: small;">Improves handling of edits to attributes and pin-map model assignments on the non-Scan page.</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4140</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adjusts ground bounce switch factor operation for pull-up/down tests.</span></li>
<li><span style="font-size: small;">Introduces option to add vectors and extend fault coverage in applications where pins share common tri-state control cells. The option is controlled by the &ldquo;Alternate drive on pins having common control cells&rdquo; check box on the settings page and the default setting is enabled. </span></li>
<li><span style="font-size: small;">Ensures that all eligible pins alternate drive on nets having multiple scan pins.</span></li>
<li><span style="font-size: small;">Corrects problem showing all LogicPinMap models on the non-Scan page.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4139</strong></big></td>
<td>Ease-of-use adjusments</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4138</strong></big></td>
<td><span style="font-size: small;">Revises and extends the manner in which the Save Test Reports option works on the Mfg Test screen</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4137</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Improves operation of JTAG Chain Auto Detect.</span></li>
<li><span style="font-size: small;">Adds support for ground debounce switch factor for pull-up/down tests.<br />
                    </span></li>
<li><span style="font-size: small;">Adds protection for test settings in the ProScan environment.</span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4136</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds support for <i>return</i> instruction in DTS model subroutines.</span><span style="font-size: small;"><br />
                    </span></li>
<li><span style="font-size: small;">Updates and expands on-line help. </span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4135</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Adds support for use of local variables within subroutines.</span><span style="font-size: small;"><br />
                    </span></li>
<li><span style="font-size: small;">Adds corrections for test status messages when stopping a test. <br />
                    </span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4134</strong></big></td>
<td><span style="font-size: small;">Upgrades test vector generation for ground debounce settings greater than one.</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4133</strong></big></td>
<td><span style="font-size: small;">Adds safeguards to prevent problems accessing dot fail files when running onTAP DLLs.<br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4132</strong></big></td>
<td>
<ul>
<li><span style="font-size: small;">Includes inductors in tests solutions and treats inductors as low impedance resistors.</span><span style="font-size: small;"><br />
                    </span></li>
<li><span style="font-size: small;">Corrects problem with test generation involving low impedance devices. </span></li>
</ul>
</td>
</tr>
<tr>
<td width="95"><big><strong>Build 4131</strong></big></td>
<td><span style="font-size: small;">Additional corrections made for Test Status text&nbsp; as well as shorts test coverage in applications having bus transceiver models<br />
                </span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4130</strong></big></td>
<td><span style="font-size: small;">Corrects test message shown in the Test Status column of the Test screens when the Retries on Fail value is greater than zero and a test failure occurs when multiple SVF files are selected.</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4129</strong></big></td>
<td><span style="font-size: small;">Adds loopback cable test, in the Cables menu, for the dual channel 30Mhz cable and restores loopback test for the single channel 6Mhz cable.</span></td>
</tr>
<tr>
<td width="95"><big><strong>Build 4128</strong></big></td>
<td><span style="font-size: small;">Provides additional correction for transceiver management during test generation</span></td>
</tr>
</tbody>
</table>
<p>&nbsp;</p>
]]></content:encoded>
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		<title>Boundary Scan Software Evaluation Download</title>
		<link>http://www.flynn.com/messages/boundary-scan-software-evaluation-download/</link>
		<comments>http://www.flynn.com/messages/boundary-scan-software-evaluation-download/#comments</comments>
		<pubDate>Wed, 03 Aug 2011 14:00:01 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Messages]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=2536</guid>
		<description><![CDATA[Thank you for your interest in onTAP&#160;Boundary Scan software.&#160; Please download and install onTAP Boundary Scan Software on your target machine.&#160; Once you install onTAP, open and run the software.&#160; This will generate a license.txt file.&#160; Please copy this file and e-mail it to license@flynn.com.&#160; We will activate your license and return a complete onTAP&#160;Boundary [...]]]></description>
			<content:encoded><![CDATA[<p>Thank you for your interest in onTAP&nbsp;Boundary Scan software.&nbsp; Please download and install onTAP Boundary Scan Software on your target machine.&nbsp; Once you install onTAP, open and run the software.&nbsp; This will generate a license.txt file.&nbsp; Please copy this file and e-mail it to<a href="javascript:location.href='mailto:'+String.fromCharCode(108,105,99,101,110,115,101,64,102,108,121,110,110,46,99,111,109)+'?'"> license@flynn.com</a>.&nbsp; We will activate your license and return a complete onTAP&nbsp;Boundary Scan Software Evaluation.&nbsp; We will also e-mail you with instructions on how to install and start developing tests with onTAP&nbsp;Boundary Scan Software.&nbsp;</p>
<p>Please click the &quot;<strong>Download Now</strong>&quot; button below to continue with the download.</p>
<p><big><strong>Current build 4300. Updated January 11, 2012. </strong></big></p>
<p><big><strong><em>Featuring: ShowMe! </em>Finally, accurate pin-level diagnostics for memory cluster test debugging!<br />
</strong></big></p>
<p><a href="http://flynn.com/files/downloads/ontap_setup.exe"><img height="24" width="127" src="/wp-content/uploads/image/PICS/download.gif" alt="Download onTAP Boundary Scan Software, begin testing today!" /></a><a href="http://flynn.com/files/downloads/ontap_setup.exe"><br />
</a></p>
<p>&nbsp;</p>
<p><span style="font-size: larger;"><strong>IMPORTANT&nbsp;NOTE: </strong></span></p>
<div style="text-indent: -0.25in; margin-right: 1.5pt;"><span style="font-size: 11pt;">&middot;<span style="font: 7pt 'Times New Roman';">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </span></span><span style="font-size: 11pt;">onTAP&nbsp;builds 4217 and later include Microsoft Visual Studio redistributable DLLs in installation package so that onTAP should run without the MS redistributable. However, if there are DLL complaints when loading onTAP, please run the MS redistributable at this link:</span></div>
<div style="text-indent: -0.25in; margin-right: 1.5pt;">&nbsp;</div>
<div style="text-indent: -0.25in; margin-right: 1.5pt;"><span style="font-size: 11pt;">&nbsp;&nbsp;&nbsp;&nbsp; <a href="http://www.microsoft.com/downloads/en/details.aspx?familyid=A7B7A05E-6DE6-4D3A-A423-37BF0912DB84&amp;displaylang=en">http://www.microsoft.com/downloads/en/details.aspx?familyid=A7B7A05E-6DE6-4D3A-A423-37BF0912DB84&amp;displaylang=en</a></span></div>
<p>&nbsp;</p>
<p><a href="/wp-content/uploads/file/onTAP%20Installation%20instructions.pdf" target="_blank"><span style="color: rgb(0, 0, 128);"><strong>VIEW&nbsp;INSTALLATION&nbsp;INSTRUCTIONS</strong></span></a> <img height="16" width="16" src="/wp-content/uploads/2008/09/pdf_symbol.gif" class="alignnone size-medium wp-image-253" title="pdf_symbol" alt="" /></p>
<p>&nbsp;</p>
<p><a href="http://www.flynn.com/boundary-scan-products-and-services/ontap-turn-key-service/"><strong>Please click here to learn more about our Turnkey&nbsp;Boundary Scan Solutions</strong></a></p>
<p><b>&quot;This [BLADE&nbsp;Network&nbsp;Research] is the second company I&rsquo;ve used onTAP at, I&rsquo;ve been using it for 3 or 4 years. Other vendors I&rsquo;ve used tended to dismiss my problems or suggest a work around that just hides the problem. Lately I&rsquo;ve been letting Flynn develop our applications because I just don&rsquo;t have the time.&nbsp; That&rsquo;s another option if you need a boundary scan test but have way too many other testing details to sort out.&quot; F. Roberts &#8216;Test Engineer&#8217; Blade Network Research<i><br />
</i></b></p>
<p><a href="http://flynn.com">Continue browsing</a></p>
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		<title>Flynn Systems Selects Keyware Technology Co., Ltd. as Chinese onTAP Reseller</title>
		<link>http://www.flynn.com/press-releases/flynn-systems-selects-keyware-technology-co-ltd-as-chinese-ontap-reseller/</link>
		<comments>http://www.flynn.com/press-releases/flynn-systems-selects-keyware-technology-co-ltd-as-chinese-ontap-reseller/#comments</comments>
		<pubDate>Tue, 02 Aug 2011 17:55:39 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[onTAP JTAG Blog]]></category>
		<category><![CDATA[Press Releases]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=3259</guid>
		<description><![CDATA[&#160; &#160;&#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160;&#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; [...]]]></description>
			<content:encoded><![CDATA[<p>&nbsp;</p>
<p style="text-align: center; ">&nbsp;&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;<img alt="onTAP Boundary Scan/JTAG Software logo" width="150" height="67" src="http://www.flynn.com/wp-content/uploads/image/logos/onTAP%20LOGO%20BSCAN%20copy.jpg" />&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;&nbsp;<img alt="Keyware Technology Co., Ltd Chinese onTAP reseller" width="160" height="50" src="http://www.flynn.com/wp-content/uploads/image/logos/Keyware%20Logo.jpg" />&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;</p>
<p><b><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">Nashua, NH August, 2011</span></b><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">&nbsp;&ndash; Flynn Systems Corp (FSC), developer of onTAP Boundary Scan Solutions, and Keyware Technology Co., Ltd. the Chinese software test technology leader in strategies and development of boundary scan and functional test, have established a new strategic relationship.&nbsp;Flynn Systems&rsquo; has made Keyware Technology Co., Ltd. their new onTAP Boundary Scan Solutions<i>&nbsp;Value Added Service Reseller </i>in China<i>.&nbsp;</i>&nbsp;Serving both domestic and international customers, Keyware Technology Co., Ltd. is located in Beijing, China. Keyware provides complete JTAG tutorial and customer consulting, DFT and JTAG test program development support for onTAP in conjunction with its functional and software test services. &nbsp;To assist Keyware in expanding its boundary scan test offerings, FSC is providing a complete suite of onTAP Boundary Scan hardware and software, along with technical support to enable Keyware to develop and run comprehensive JTAG tests using onTAP Boundary Scan Series 4000.</span></p>
<div style="<br />
line-height:14.25pt"><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">Current and potential Chinese customers of onTAP Boundary Scan Solutions are encouraged to use Keyware as a resource for rapid, responsive, full service test solutions.&nbsp;Ryan Flynn, FSC&rsquo;s Marketing Manager says, &ldquo;This is a terrific opportunity for Flynn Systems.&nbsp;We are excited to work with such a dynamic and competent group like Keyware. Keyware has demonstrated deep working knowledge of onTAP and is known for helping customers by simplifying test strategies while giving the best overall test solutions. We believe working with Keyware offers Chinese users of onTAP more options for sales and support, and ultimately a broader range of test development services.&nbsp;We are confident in their capabilities, in their tests and the high level of customer service they deliver to our mutual customers.&rdquo;</span></div>
<div style="<br />
line-height:14.25pt">&nbsp;</div>
<div style="<br />
line-height:14.25pt"><b><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">KEYWARE</span></b><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">&nbsp;(</span><span style="font-size:10.0pt;Verdana&quot;,&quot;sans-serif&quot;;"><span style="font-size:12.0pt;Calibri&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;"><a href="http://www.keyware.com.cn">http://www.keyware.com.cn</a></span>) </span><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">is a leading developer and supplier of JTAG test solutions in China and Taiwan. Keyware is a team of software test experts and engineers focused on delivering precise and robust solutions. Keyware provides boundary scan /JTAG and functional test sales and support for many diverse industries including high tech, medical, green tech, gaming, and defense. </span></div>
<div style="<br />
line-height:14.25pt">&nbsp;</div>
<ul>
<li><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">Design-For-Testability (DFT) analysis including checking the DFT compliance of customer&rsquo;s design before board layout. onTAP&nbsp;Boundary Scan/(JTAG) test program development, including on-board programming of CPLD, FPGA, flash, I<sup>2</sup>C, IEEE 1149.6&nbsp;</span></li>
<li><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;color:#454545">Chinese language sales and support team trained in using onTAP tools for a full range of boundary scan applications.</span></li>
</ul>
<div style="<br />
margin-left:-10.5pt;line-height:14.25pt"><b><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;<br />
color:#454545">Flynn Systems Corp.</span></b><span style="font-size:12.0pt;Arial&quot;,&quot;sans-serif&quot;;Times New Roman&quot;;<br />
color:#454545">&nbsp;(<a href="http://www.flynn.com/"><b><span style="color:#0066CC">www.flynn.com</span></b></a>)&nbsp;has provided test, debug, and programming solutions for the Boundary Scan test standard (JTAG IEEE 1149.1 &ndash; 6) for over ten years.&nbsp;Their onTAP software package delivers completely automated Boundary Scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-Boundary Scan devices interacting with the scan enabled devices.&nbsp;onTAP&rsquo;s functionality also includes the capability to program flash devices using only the onTAP USB Test and Programming Cable. Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. &nbsp;Its satisfied customers include Intel, Qualcomm, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona.&nbsp; Flynn Systems&rsquo; onTAP provides Boundary Scan services for university research, avionics, defense systems, consumer goods, and medical electronics.&nbsp; It is based in New Hampshire with distributors and partners in Europe and in the Middle East, and now China.</span></div>
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		<title>onTAP SUMMER SALE!!!</title>
		<link>http://www.flynn.com/product-news/ontap-summer-sale/</link>
		<comments>http://www.flynn.com/product-news/ontap-summer-sale/#comments</comments>
		<pubDate>Wed, 22 Jun 2011 21:56:09 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[onTAP JTAG Blog]]></category>
		<category><![CDATA[Product News]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=3228</guid>
		<description><![CDATA[&#160; Download the PDF by clicking here. When you purchase any onTAP Boundary Scan Software license, we are giving you the option to add another license to your package for FREE*.&#160; That&#8217;s right, FREE!&#160; Buy a development seat for the lab, or an MTO for manufacturing, and get another one for a co-worker. You have [...]]]></description>
			<content:encoded><![CDATA[<p><img src="http://www.flynn.com/wp-content/uploads/image/PICS/SUMMER%20SALE.jpg" alt="Free boundary scan jtag software" style="width: 576px; height: 164px;" /></p>
<p>&nbsp;</p>
<div style="line-height: normal;"><a href="http://www.flynn.com/wp-content/uploads/onTAP SUMMER SALE.pdf">Download the PDF by clicking here.</a></div>
<div style="line-height: normal;"><b><span style="font-size: 12pt;">When you purchase any onTAP Boundary Scan Software license, we are giving you the option to add another license to your package for FREE*.&nbsp; That&rsquo;s right, FREE!&nbsp; Buy a development seat for the lab, or an MTO for manufacturing, and get another one for a co-worker. You have your choice of an MTO or DLL.&nbsp; And, in the spirit of Summer and fun, easy living, we&rsquo;re going to make this offer even better by giving you total flexibility. We will upgrade every license purchased between June 16 and July 20 to a USB Dongle-based Portable license.</span></b></div>
<div style="margin-bottom: 0.0001pt; line-height: normal;"><b><i><u><span style="font-size: 12pt;">But, you have to act fast! This special offer is only available through July 20.</span></u></i></b><b>&nbsp;</b></div>
<div style="margin-bottom: 0.0001pt; line-height: normal;"><span style="font-size: 12pt;"><br />
We look forward to hearing from you.&nbsp; Please feel free to contact us to discuss your boundary scan application. </span></div>
<div style="margin-bottom: 0.0001pt; line-height: normal;"><span style="font-size: 12pt;"><br />
Best regards,</span></div>
<div style="margin-bottom: 0.0001pt; line-height: normal;"><span style="font-size: 12pt;">onTAP Boundary Scan Sales Team</span></div>
<div style="margin-bottom: 0.0001pt; line-height: normal;"><span style="font-size: 12pt;"><a href="../../../../../../"><span style="color: blue;">www.flynn.com</span></a></span></div>
<div style="margin-bottom: 0.0001pt; line-height: normal;"><span style="font-size: 12pt;"><a href="mailto:sales@flynn.com"><span style="color: blue;">sales@flynn.com</span></a></span></div>
<div style="margin-bottom: 0.0001pt; line-height: normal;"><span style="font-size: 12pt;">&nbsp;+1 (603) 598-4444</span></div>
<p>&nbsp;</p>
<p>&nbsp;</p>
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		<title>Boundary Scan that Fits Your Budget</title>
		<link>http://www.flynn.com/product-news/boundary-scan-that-fits-your-budget/</link>
		<comments>http://www.flynn.com/product-news/boundary-scan-that-fits-your-budget/#comments</comments>
		<pubDate>Mon, 23 Aug 2010 19:03:42 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[onTAP JTAG Blog]]></category>
		<category><![CDATA[Product News]]></category>
		<category><![CDATA[Boundary Scan Budget]]></category>
		<category><![CDATA[Budget JTAG]]></category>
		<category><![CDATA[JTAG Software on a budget]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=3106</guid>
		<description><![CDATA[I thought it was important to post something about onTAP&#160;being the perfect boundary scan solution for any JTAG&#160;user, but especially those in budget critical situations after some weekend reading brought me across a couple of articles in Electronics Weekly about boundary scan useage and budgetary demands.&#160; One article from April 28, 2010 titled Boundary Scan [...]]]></description>
			<content:encoded><![CDATA[<p>I thought it was important to post something about onTAP&nbsp;being the perfect boundary scan solution for any JTAG&nbsp;user, but especially those in budget critical situations after some weekend reading brought me across a couple of articles in <a href="http://www.electronicsweekly.com/Home/">Electronics Weekly</a> about boundary scan useage and budgetary demands.&nbsp; One article from April 28, 2010 titled <i><u>Boundary Scan on a Budget</u> </i> <i><a href="http://www.electronicsweekly.com/Articles/2010/04/28/48512/boundary-scan-on-a-budget.htm">(http://www.electronicsweekly.com/Articles/2010/04/28/48512/boundary-scan-on-a-budget.htm</a>) </i>and another June 29, 2010 article <i><u>Agilent gets serious about JTAG test</u></i> describe how users are seeing an increased use of boundary scan brings down costs.&nbsp; However,&nbsp; the article fails to point out any real costs or even estimated costs for boundary scan tools.&nbsp; <strong>We all know that this stuff isn&#8217;t inexpensive, but how much can one expect to pay?&nbsp; </strong><u><strong>With onTAP, you will receive a complete boundary scan system for under $15,000.</strong></u> Read on for more details.</p>
<p>As you may already be aware, onTAP regularly competes with all the other boundary scan vendors, world-wide, and wins.&nbsp; In many cases, other boundary scan customers are the same as onTAP customers. &nbsp;In many other cases, onTAP has been selected to replace other boundary scan systems because of the great value and support it delivers, at a substantially lower cost, thus enabling more widespread deployment.&nbsp; &nbsp;</p>
<div>&nbsp;</div>
<div>While the other systems are sold piecemeal, onTAP is an all inclusive<strong> netlist based boundary scan</strong> system that enables users to <strong>develop and run automated interconnect tests, debug the tests</strong> using ProScan, the built-in graphical debug environment, capture pin-level diagnostic messages, view reports and edit tests.&nbsp;<strong> IEEE 1149.1 and 1149.6 compliant</strong>, onTAP also automatically accounts for AC coupled circuits.&nbsp; Moreover, onTAP enables users to develop and run reliable, reusable memory cluster tests, program flash and control I2C buses.&nbsp; There is a built-in library of buffers, resistors, and transceivers, while more complex models are kept in our library. Our models are developed free of charge and can be customized to a user&rsquo;s particular needs. &nbsp;All models are completely reusable across different projects and just as importantly, offer great flexibility making it simple to tailor to a particular user&rsquo;s needs.</div>
<div>&nbsp;</div>
<div>The models are written in a C-like language called DTS, a legacy of Flynn Systems&rsquo; GenRad and Automatic Test Generation roots, and are easily edited by any user with a simple working knowledge of C and the accompaniment of the DTS Programming Manual.</div>
<div>&nbsp;</div>
<div>That, in a nut-shell is onTAP.&nbsp; So, what makes it attractive for the value-seeking user?&nbsp; A complete onTAP Boundary Scan system is at least 20% less the lowest cost comparable product and we offer a 30 Day no obligation evaluation. &nbsp;&nbsp;<strong>The average cost of a complete onTAP Boundary Scan System, including a dual channel HighSpeed USB JTAG controller is under $15,000 USD.</strong></div>
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		<title>FSC and SSP Partner with Value Added Service Provider Agreement</title>
		<link>http://www.flynn.com/press-releases/fsc-and-ssp-partner-with-value-added-service-provider-agreement/</link>
		<comments>http://www.flynn.com/press-releases/fsc-and-ssp-partner-with-value-added-service-provider-agreement/#comments</comments>
		<pubDate>Thu, 29 Jul 2010 16:06:20 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Press Releases]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=3045</guid>
		<description><![CDATA[&#160; Nashua, NH July, 2010 &#8211; Flynn Systems Corp (FSC), developer of onTAP Boundary Scan Solutions, and Solution Sources Programming (SSP), the test technology leader in strategies and development of Benchtop Boundary Scan, ICT, and Functional Test, have established a new strategic relationship.&#160;Flynn Systems&#8217; has made Solution Sources Programming, Inc. their new onTAP Boundary Scan [...]]]></description>
			<content:encoded><![CDATA[<p>&nbsp;</p>
<p><strong><span style="font-family: Arial;"><span style="font-size: small;">Nashua, NH July, 2010</span></span></strong><span style="font-family: Arial;"><span style="font-size: small;"> &#8211; Flynn Systems Corp (FSC), developer of onTAP Boundary Scan Solutions, and Solution Sources Programming (SSP), the test technology leader in strategies and development of Benchtop Boundary Scan, ICT, and Functional Test, have established a new strategic relationship.&nbsp;Flynn Systems&rsquo; has made Solution Sources Programming, Inc. their new onTAP Boundary Scan Solutions<i> Value Added Service Provider.&nbsp;</i>&nbsp;Serving both Domestic and International Customers, SSP is located in Northern California (San Jose), SSP provides complete JTAG tutorial and customer consulting, DFT and JTAG test program development support for onTAP in conjunction with its ICT and Functionalservices. &nbsp;To assist SSP in expanding their boundary scan test offerings, FSC is providing a complete suite of onTAP Boundary Scan hardware and software, along with technical support to enable SSP to develop and run comprehensive JTAG tests using onTAP Boundary Scan Series 4000.</span></span></p>
<p>&nbsp;</p>
<p><span style="font-family: Arial;"><span style="font-size: small;"></p>
<p>Current and potential customers of onTAP Boundary Scan Solutions are encouraged to use SSP as a resource for rapid, responsive, full service test solutions.&nbsp;Ryan Flynn, FSC&rsquo;s Marketing Manager says, &ldquo;This is a terrific opportunity for Flynn Systems.&nbsp;We are excited to work with an Industry Leader like SSP, known for helping customers by simplifying test strategies but giving the best overall test solutions. We believe working with SSP offers onTAP users more options and a broader range of test development services.&nbsp;We are confident in their capabilities, in their tests and the high level of customer service they deliver to our mutual customers.&rdquo;</p>
<p></span></span><span style="font-size: small;"></p>
<p>&nbsp;</p>
<p></span><span style="font-family: Arial;"><span style="font-size: small;">    </span></span></p>
<p><strong><span style="font-family: Arial;"><span style="font-size: small;">SSP</span></span></strong><span style="font-family: Arial;"><span style="font-size: small;"> (<a href="http://www.ssprog.com">www.ssprog.com</a>) is a leading developer and supplier of JTAG test solutions in California across all hardware levels, including device, board, and system. SSP is a team of test experts and engineers. SSP serves as a Benchtop Boundary Scan /JTAG, In-Circuit Test (ICT), and Functional Test support supplier for many diverse industries like High Tech, Medical, Green Tech, Defense to name a few.</span></span></p>
<ul>
<li><span style="font-family: Arial;"><span style="font-size: small;">Design-For-Testability (DFT) analysis including checking the DFT compliance of customer&rsquo;s design before board layout. onTAP&nbsp;Boundary Scan/(JTAG) test program development, including on-board programming of CPLD, FPGA, flash, I<sup>2</sup>C, IEEE 1149.6 <br />
    </span></span></li>
<li><span style="font-family: Arial;"><span style="font-size: small;"><span style="line-height: 115%;">ICT test program development for the Agilent 307X and Teradyne TS and 228X testers</span></span></span></li>
<li><span style="font-family: Arial;"><span style="font-size: small;"><span style="line-height: 115%;">Functional test program development and system architecture utilizing Agilent and LabView software/hardware solutions; and incorporating Boundary Scan into functional applications</span><span style="line-height: 115%;">. </span></span></span></li>
</ul>
<p><strong><span style="font-family: Arial;"><span style="font-size: small;">Flynn Systems Corp.</span></span></strong><span style="font-family: Arial;"><span style="font-size: small;"> (<a href="http://www.flynn.com">www.flynn.com</a>) <span style="line-height: 115%;">has provided test, debug, and programming solutions for the Boundary Scan test standard (JTAG IEEE 1149.1 &#8211; 6) for over ten years.&nbsp;Their onTAP software package delivers completely automated Boundary Scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-Boundary Scan devices interacting with the scan enabled devices.&nbsp;onTAP&rsquo;s functionality also includes the capability to program flash devices using only the onTAP USB Test and Programming Cable. Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. &nbsp;Its satisfied customers include Intel, Qualcomm, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona.&nbsp; Flynn Systems&rsquo; onTAP provides Boundary Scan services for university research, avionics, defense systems, consumer goods, and medical electronics.&nbsp; It is based in New Hampshire with distributors and partners in Europe and in the Middle East.</span></span></span></p>
<p>&nbsp;</p>
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		<title>onTAP Supports IEEE 1149.6!</title>
		<link>http://www.flynn.com/product-news/ontap-is-ieee-1149-6-enabled/</link>
		<comments>http://www.flynn.com/product-news/ontap-is-ieee-1149-6-enabled/#comments</comments>
		<pubDate>Fri, 14 May 2010 20:26:45 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[onTAP JTAG Blog]]></category>
		<category><![CDATA[onTAP Usage]]></category>
		<category><![CDATA[Press Releases]]></category>
		<category><![CDATA[Product News]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=2979</guid>
		<description><![CDATA[As we have promised our users, Flynn Systems continues to develop and add new features to onTAP Boundary Scan Software.&#160; These new features vastly improve onTAP&#8217;s capability, enabling onTAP&#160;users to do more with less.&#160; We had been developing support for IEEE 1149.6 for several months, and at the end of April, we were able to [...]]]></description>
			<content:encoded><![CDATA[<p>As we have promised our users, Flynn Systems continues to develop and add new features to onTAP Boundary Scan Software.&nbsp; These new features vastly improve onTAP&#8217;s capability, enabling onTAP&nbsp;users to do more with less.&nbsp; We had been developing support for IEEE 1149.6 for several months, and at the end of April, we were able to fully implement the IEEE 1149.6 standard into the current version of onTAP.&nbsp; It has been rigorously field tested, and we are proud to release it to our user community. Please download the newest version of onTAP, and feel free to begin developing truly complete, robust JTAG&nbsp;tests for your projects with IEEE 1149.6 capability.</p>
<p><span style="font-size: larger;"><strong>onTAP Boundary Scan Software Now Supports IEEE 1149.6</strong></span></p>
<div>&nbsp;</div>
<div><strong><span style="font-size: 11pt;">NASHUA, NH</span></strong><span style="font-size: 11pt;"> May 14, 2010 &#8211; Flynn Systems Corp is proud to announce the latest version of onTAP is IEEE 1149.6 compliant.&nbsp;The implementation of IEEE 1149.6 greatly enhances onTAP&rsquo;s scope and capability, while delivering more JTAG test coverage and power to current and interested onTAP users. </span></div>
<div>&nbsp;</div>
<div><span style="font-size: 11pt;">According to Ryan Flynn, onTAP Marketing Manager, &ldquo;As Xilinx and Altera begin to implement IEEE 1149.6 protocols in their latest designs, including the Virtex 6 and Aria GX devices (respectively), it was increasingly important for us to enable onTAP users with every bit of capability so they could harness the full test potential of these new devices and implement them into their designs.&nbsp;onTAP&rsquo;s IEEE 1149.6 implementation has been field tested in very intense and rigorous applications with Intel.&nbsp;Intel&rsquo;s success has been a heck of proving ground for onTAP.&rdquo;</span></div>
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<div><span style="font-size: 11pt;">As implementation of IEEE 1149.1 and 1149.X Boundary Scan testing becomes more widespread, greater flexibility, faster speeds, and smoother operation are needed.&nbsp;Flynn Systems&rsquo; commitment to its Customers has always been to keep onTAP a live software by continuing to support, develop, and enhance onTAP tools that capitalize on JTAG test capability. The 1149.6 implementation is another demonstration of Flynn&rsquo;s commitment to its user base. </span></div>
<div><span style="font-size: 11pt;">onTAP&rsquo;s new update expands users&rsquo; test capabilities, flexibility, and further enhances test fault coverage in a number of ways.&nbsp;Most apparent is the productivity gain achieved by testing to both IEEE 1149.1 and IEEE 1149.6 standards.&nbsp;The IEEE 1149.6 feature enables users to test AC Coupled circuits and differential pairs to the industry standard protocol.&nbsp;Adding these two elements to a test not only increases test fault coverage, but also creates a more robust and reliable test by incorporating additional aspects of the board in the test. </span></div>
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<div><span style="font-size: 11pt;">Flynn Systems continues its pursuit of delivering cost-effective, complete, robust JTAG test and programming software packages with attentive and dedicated technical support to its current users and anyone interested in a feature-rich, high-value complete JTAG solution at a reasonable price. </span></div>
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<div><b><span style="">About Flynn Systems:</span></b></div>
<div><span style="">Flynn Systems began delivering Automatic Test Generation Solutions to the ATE market as FS-ATG in 1986.&nbsp;In late 1999, they transitioned to the boundary scan market with onTAP and have provided test, debug, and programming solutions for the boundary scan test standard (JTAG IEEE 1149.1) for over ten years.&nbsp;Their onTAP software package is designed for completely automated boundary scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-boundary scan devices interacting with the scan enabled devices.&nbsp;onTAP&rsquo;s functionality also includes the capability to program FLASH devices using only the onTAP USB Test and Programming Cable (HighSpeed included). Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support.&nbsp;Its satisfied customers include Intel, Qualcom, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona.&nbsp;Flynn Systems&rsquo; onTAP provides boundary scan services for university research, avionics, defense systems, consumer goods, and medical electronics.&nbsp;It is based in New Hampshire with distributors and partners in Europe and Asia. </span></div>
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<div><span style="">Those interested are invited to download a free 30 day evaluation software package with full technical support available at </span><a href="../../../../../../"><span style="">www.flynn.com</span></a><span style="">.</span></div>
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		<title>Groundhog Day Sale</title>
		<link>http://www.flynn.com/jtag-blog/ground-hogs-day-sale/</link>
		<comments>http://www.flynn.com/jtag-blog/ground-hogs-day-sale/#comments</comments>
		<pubDate>Tue, 02 Feb 2010 21:30:37 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[onTAP JTAG Blog]]></category>
		<category><![CDATA[boundary scan]]></category>
		<category><![CDATA[Free JTAG]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=2845</guid>
		<description><![CDATA[When you purchase any onTAP Boundary Scan Software license, we are giving you the option to add another license to your package for FREE*.  That’s right, FREE.  Buy a development seat for the lab, or an MTO for manufacturing, and get another one for a co-worker. You have your choice of an MTO or DLL.  ]]></description>
			<content:encoded><![CDATA[<p>&nbsp;</p>
<p style="text-align: center;"><img src="/wp-content/uploads/image/PICS/GHD2010.bmp" style="width: 351px; height: 240px;" alt="" /></p>
<p style="text-align: center;"><img width="427" height="77" src="/wp-content/uploads/image/PICS/onTAPS400img.jpg" alt="" /><br />
EVERYTHING&nbsp;YOU&nbsp;NEED</p>
<p style="text-align: left;">&nbsp;</p>
<div><b>Nashua, NH</b> by-way-of <b>Gobbler&rsquo;s Nob, Punxsutawney, Pennsylvania</b> &ndash; Well, it&rsquo;s official! The groundhog poked out and saw its shadow.&nbsp; Settle in for six more weeks of winter.&nbsp; The upside is, you have six more weeks to not worry about nice sunny days and walks in the park with sunshine on your face.&nbsp; That means more winter time to dedicate to developing and debugging your projects so when spring does finally arrive, you&rsquo;re ready to take full advantage of the nice spring weather.</div>
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<div>We know you&rsquo;re busy, but bargains are always welcome.&nbsp; Flynn Systems is announcing its Groundhog Day Special.</div>
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<div>Even though we all got the bad news that winter is continuing for six more weeks, we want to give you some good news about boundary scan test tools.&nbsp; When you purchase any onTAP Boundary Scan Software license, we are giving you the option to add another license to your package for FREE*.&nbsp; That&rsquo;s right, FREE.&nbsp; Buy a development seat for the lab, or an MTO for manufacturing, and get another one for a co-worker. You have your choice of an MTO or DLL.&nbsp;</div>
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<div>Act fast, this offer only lasts until the first official day of spring &ndash; March 20, 2010</div>
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<div><span style="">We look forward to hearing from you.&nbsp; Please feel free to contact us to discuss your boundary scan application. </span></div>
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<p><span style="font-size: smaller;">THE&nbsp;SMALL&nbsp;PRINT:</span></p>
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<div><span style="font-size: small;">*Free onTAP software offer applies to all quotes generated between Feb. 2 2010 and March 20, 2010 and is limited to one free license per quote.&nbsp;Offer is also limited to either an MTO or DLL.&nbsp;Offer expires on March 20, 2010.</span></div>
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		<title>Happy New Year &#8211; Welcome 2010</title>
		<link>http://www.flynn.com/jtag-blog/happy-new-year-welcome-2010/</link>
		<comments>http://www.flynn.com/jtag-blog/happy-new-year-welcome-2010/#comments</comments>
		<pubDate>Mon, 18 Jan 2010 17:40:17 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[onTAP JTAG Blog]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=2811</guid>
		<description><![CDATA[We hope everyone is off to a strong and promising 2010.&#160;&#160; By all signs, it appears that this year will deliver new innovations and products to the electronics market.&#160; We certainly are excited to hear about our customers new projects and are looking forward to sharing our new developments with you through out the course [...]]]></description>
			<content:encoded><![CDATA[<p>We hope everyone is off to a strong and promising 2010.&nbsp;&nbsp; By all signs, it appears that this year will deliver new innovations and products to the electronics market.&nbsp; We certainly are excited to hear about our customers new projects and are looking forward to sharing our new developments with you through out the course of this exciting new year.</p>
<p>Keep an eye for some major upgrades to the software that are sure to greatly increase test capability, usability, and productivity.</p>
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<p>Here&#8217;s to a successful and prosperous 2010!</p>
<p>&nbsp;</p>
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		<title>Properly Managing Common Tri-State Control Cells Boosts Fault Coverage</title>
		<link>http://www.flynn.com/jtag-blog/properly-managing-common-tri-state-control-cells-boosts-fault-coverage/</link>
		<comments>http://www.flynn.com/jtag-blog/properly-managing-common-tri-state-control-cells-boosts-fault-coverage/#comments</comments>
		<pubDate>Wed, 16 Dec 2009 20:16:00 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[onTAP JTAG Blog]]></category>
		<category><![CDATA[onTAP Usage]]></category>
		<category><![CDATA[boundary scan]]></category>
		<category><![CDATA[Boundary Scan JTAG Turnkey Solution]]></category>
		<category><![CDATA[boundary scan test]]></category>
		<category><![CDATA[boundary scan test types]]></category>
		<category><![CDATA[DFT and JTAG test]]></category>
		<category><![CDATA[JTAG]]></category>
		<category><![CDATA[JTAG boundary scan test]]></category>
		<category><![CDATA[JTAG Test]]></category>
		<category><![CDATA[turnkey JTAG test]]></category>

		<guid isPermaLink="false">http://www.flynn.com/?p=2800</guid>
		<description><![CDATA[ We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.]]></description>
			<content:encoded><![CDATA[<p><span style="font-size: small;">As the boundary scan community continues looking for new ways to improve test procedures and achieve higher and higher fault coverage, we expect the test tools to compensate for shortcomings in silicon devices or board design.&nbsp;We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage.&nbsp;One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.</span></p>
<p><span style="font-size: small;">  <span style="line-height: 115%;">Common tri-state control cells are groups of pins on a common net.&nbsp; Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell.&nbsp;Though this is efficient for circuitry, it poses some issues during JTAG test.&nbsp;For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously.&nbsp;This is represented in the following drawing.</span></span></p>
<p><img src="file:///C:/Users/Ryan/AppData/Local/Temp/moz-screenshot-4.png" alt="" /></p>
<p><img src="file:///C:/Users/Ryan/AppData/Local/Temp/moz-screenshot-5.png" alt="" /></p>
<p><img width="414" height="174" alt="Tri-State Control Cell diagram for JTAG test" src="/wp-content/uploads/image/PICS/Tri-State%20Control%20Cells.jpg" /><br />
Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below.&nbsp;</p>
<p><img width="541" height="170" alt="onTAP JTAG Test showing Common Tri-State Control Cell un-tested" src="/wp-content/uploads/image/PICS/BLOG%20POSTS/ProScan%20no%20TriState.jpg" /><br />
<var>In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage. </var></p>
<div><span style="font-size: small;"><var>The yellow 0 and 1 characters show drive, or boundary register update, values at each test vector, and the green L and H values show expected boundary register capture values on the vectors following an update.</p>
<p></var></span></div>
<p><img width="605" height="197" alt="Mv64360 boundary scan device multiple pins sharing common tr-state cells" src="/wp-content/uploads/image/PICS/BLOG%20POSTS/Mv6430%20TriState.jpg" /><var><span style="font-size: small;"><br />
</span></var></p>
<p><var><span style="font-size: small;">This image shows the netlist view of the Mv6430 <strong>boundary scan</strong> device, while the following image displays the pins in an expanded view.</span></var></p>
<p><img width="621" height="241" alt="onTAP Netlist Browser displays common tristate control cells for JTAG device" src="/wp-content/uploads/image/PICS/BLOG%20POSTS/Mv6430%20TriState%20Netsview.jpg" /></p>
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<p><img width="624" height="117" alt="ProScan test view showing additional vectors added to JTAG test for tristate condition" src="/wp-content/uploads/image/PICS/BLOG%20POSTS/tristate%20fixed.jpg" /></p>
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<div><var><span style="font-size: small;"><em>This image shows how the test was revised to account for the tri-state pins on the common control cell. &nbsp;The result is a boost in fault coverage, with the added benefit of making the test more accurate.</em></span></var></div>
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<div>As explained in the text box in this screen shot, onTAP accounts for the shared cells and adds additional test vectors to ensure pins do not drive simultaneously, allowing for more comprehensive tests that deliver higher, and most importantly, more accurate, test fault coverage.&nbsp;</div>
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