How to obtain a VHD netlist output file, based upon logic primitive declarations using Xilinx ISE

1. From a Command Prompt run the following: -ofmt vhdl -a -fn -log ngd2vhdl.log tmicro.nga tmicroTest.vhd
2. Open the Implement tree.
3. Open the FIT tree.
4. Run the Lock Pins routine.
5. Run the Generate Timing routine.
6. Run the Generate Post-FIT simulation model. (This creates the NGA file)

7. From a Command Prompt, run the following:
   ngd2edif -a -hpn <input.nga> <output.edn>
   (The input.nga file will have the name of the top-level VHDL entity)

8. Copy this file to your FS-ATG Project directory.
   
   (These instructions provided courtesy of Ron Kralik, FS-ATG test users at Becton-Dickson and Company, Sparks, MD.)