• how to obtain a flattened edif netlist using Xilinx Alliance M-1
• how to obtain an XNF using Xilinx Xact
• known issues using Xilinx Alliance M-1

How to obtain a flattened edif netlist using Xilinx Alliance M-1

The .EDN is a flattened edif netlist file.

1. From your design entry tool, output the design as EDF, EDIF, SEDIF, PLD, SXNF, XNF, or XTF file. Note that the PLD format is available only for XC7300 and XC9500 device families only.
2. In the Xilinx Design Manager, open an existing project file or create a new project file into which to import your logic design.
3. Select Design --> Implement. If you wish, you can choose a different target device in which to implement your design. The initial target device is specified in the input design or when you create a new implementation revision.
4. Select an option template to specify implementation/configuration options. You can use the default template, an existing template, or define a new template.
5. Process your design and create the Timing Simulation Files and the Device Programming file. To do this, In the Implementation Window, Click OPTIONS. From there, select "Produce Timing Simulation Data" and "Produce Configuration Data."
6. Select EDIT TEMPLATE-->Simulation. There are three TABS to choose from. Select EDIF. Deselect <Retain Hierarchy in Netlist>. This option allows the Design Manager to compile the edif netlist as a flattened file.

   Review the design reports to verify that your design fits within the target device and that your timing requirements are met. If they are not met, then reprocess your design and change your logic design. You also have the option to choose a different target device, package, speed grade, or define a different set of implementation options.

   The flattened netlist file is in the following location: \\\time_sim.edn. Copy this file to your FS-ATG Project directory and rename the file to match your desired design name.

How to obtain an XNF using Xilinx Xact

The .XNF file is a flattened Xilinx netlist format file. XNF files, to be used with FS-ATG, can be created using Xilinx XACT, older revs of the Xilinx M1, or any Xilinx-compatible design software that includes the .XNF translator. For Xilinx XC2000, XC3000, XC4000, XC5200, & XC9500 devices, .XNF files must be created using the LCA2XNF utility. LCA2XNFconverts Logic Cell Array (.LCA) files into the Xilinx netlist format (.XNF) files. The LCA2XNF utility can be run either from the XACT Design Manager or a DOS prompt.

1. If running XACT Design Manager, go to Convert menu. Select LCA2XNF.
2. Specify the LCA file to be converted and select DONE.
3. If running from a DOS prompt from within the XACT directory, run:
   LCA2XNF -g <filename.LCA>
4. If the .LCA file was created using NeoCad software, include both the -v & -g switches on the LCA2XNF command line, as follows:
   c:\> LCA2XNF -v -g <filename.LCA>
   

   For Xilinx 7000 devices, .XNF files are created with the VMH2XNFutility, using the .VMH file, instead of the .LCA file, as input.
   

5. From the XACT Design Manager Verify menu, select VMH2XNF.
6. Specify the .VMH file to be converted and select DONE.
7. With the Xilinx M1 software, .XNF files are created with the NGD2XNFutility. This is done by using the .NGD instead of the .LCA as an input file.

Known issues using Xilinx Alliance M-1

1. Missing PIN designators

   There have been occurrences where the edif netlist is missing PIN designators. This can occur for many reasons. Once particular instance has been documented. When the top-level edif netlist was generated, using the ABL2EDIF translator, without the -s top switch extension, pin designators were not included in the edif netlist. The proper translation requires the use of the -s top switch extension. In order for the Xilinx edif netlist to work properly with FS-ATG, all pin designators must be accounted for.

2. Non-flattened edif netlists

   Non-flattened netlists occur when <Retain Hierarchy in Netlist> is not deselected during the IMPLEMENT phase of compilation. See section on how to obtain a flattened edif netlist to correct this problem.