The .VHD file is a VHDL structural-style netlist. The .XRF file relates signal names to external pin names. The following procedure applies to MACHXL 5.2 for Windows platforms.

1. From the MACHXL menu, select FILE. Open the .SRC file for the project. The .SRC file will appear on the screen in ULTRA-EDIT. Close both the .SRC file window and ULTRA-EDIT window.
2. From the top menu bar, select PROJECT. The .SRC file is now the design file ready to be compiled/optimized.
3. Select COMPILE/OPTIMIZE. From the pop-up window, select DESIGN to compile the design. If no errors occur, close the COMPILE screen. Any errors in the .SRC file must be fixed before continuing.
4. Select SETTINGS. In the AUTHORIZATION and OPTIONS window, select OPTIONS.
5. In the next window select the TIMING MODELS folder. In the TIMING MODELS folder, specify these settings: Output type is 'VHD (generic), Standard'. On the MODGEN application command line, place XRF. Click OK.
6. From the top menu bar, select PROJECT --> PARTITION/FIT. Two menus will appear during this operation. In the first menu, select the correct device type. Click OK.
7. In the next menu, select the correct package type. Click OK. Once partitioning and fitting completes, select DESIGN TIMING MODELS to run the MODGEN utility. (MODGEN must be 3.6b or higher.)
8. The resultant .VHD & .XRF files will be placed in the sub-directory 'models'. These files are ready for use with FS-ATG.