• Cooperative boundary-scan test development
• Cluster test model development for testing of non-jtag memory and flash devices
• Design for Testability (DFT) recommendations for board re-designs
• Expert evaluation of your board test results and online assistance with debug.
• BSDL syntax verification to IEEE 1149.1b Boundary Scan Specification

Our test development process takes advantage of your working knowledge of your board designs and our onTAP test development expertise to produce the highest quality tests, completed more quickly and economically.

When you send us your BSDL and CAD netlist files, plus datasheets for any non-jtag memory and FLASH devices you want to test, we then work closely with you via email and telephone and develop your onTAP boundary scan tests. Then, when you are ready to apply the tests to the board, we are at your service to assist you as you debug your test, and revise it as necessary to deal with unanticipated board-level and device interactions.

From our experience in developing hundreds of successful boundary scan tests with customers all over the world, we have found this methodology to produce the most consistently successful test results.

Cooperative boundary-scan test development

Cluster test model development for testing of non-jtag memory and flash devices

Design for Testability (DFT) recommendations for board re-designs

Expert evaluation of your board test results and online assistance with debug.

BSDL syntax verification to IEEE 1149.1b Boundary Scan Specification
Our test development process takes advantage of your working knowledge of your board designs and our onTAP test development expertise to produce the highest quality tests, completed more quickly and economically.

When you send us your BSDL and CAD netlist files, plus datasheets for any non-jtag memory and FLASH devices you want to test, we then work closely with you via email and telephone and develop your onTAP boundary scan tests. Then, when you are ready to apply the tests to the board, we are at your service to assist you as you debug your test, and revise it as necessary to deal with unanticipated board-level and device interactions.

From our experience in developing hundreds of successful boundary scan tests with customers all over the world, we have found this methodology to produce the most consistently successful test results.

Overview of the Test Development Procedure

Step 1. You send us your board netlist, BSDLs, and datasheets for any non-jtag devices you want to include as a cluster test. Cluster testing non-jtag devices can boost your overall fault coverage tremendously.

Step 2. We generate the test program and the cluster test device models for devices on your board. This step usually requires some back and forth with you to set jumpers and guards to deal with the various interactions between devices on your board.

Step 3. You apply the tests to the board at your facility and let us assist in your test and board debugging. We can show you how to use onTAP's diagnostic tools to get visibility into the state of each boundary cell at each scan vector, and single step through the test. We can assist you in interpreting the diagnostics and edit/regenerate the tests as required.

Pricing and Lead Time

Pricing for this service is dependent upon the complexity of your board.
For a pricing estimate, please send us:

Board netlist
BSDL files for all boundary scan devices on your board.
Datasheets for any non-jtag devices that you wish to cluster test.
Test development lead time ranges from 2 days to 2 weeks depending upon the complexity of the board and the number of cluster test models required.