Common tri-state control cells are groups of pins on a common net.  Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.

Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below. 

In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.

This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.

How onTAP Detects and Diagnoses Mid-State Shorts

Mid-state shorts are bridging faults that result in a mid-state voltage level rather than a hard low or high level. In our experience at Flynn Systems when working with customers, we have found the condition occurs where short circuits exist:

1. between some boundary-scan pins on FPGA devices when only one boundary scan pin is present on a PCB net
2. across pins on resistor networks where the resistors lie between the shorts fault and scannable pins, and again on nets that have only one boundary-scan pin

Mid-state shorts, like any bridging fault, can result in system level applications failures if not detected and cleared. The difficulty is that these shorts will not be detected by traditional boundary scan shorts detection algorithms where zero or one logic levels must be detected. The reason is that at the capture cell on single-pin nets, the capture value is equal to the value being actively driven from the same pin.

In the case of the resistor network, it is easy to see how the resistors can isolate the capture value from the value measured at the physical short. In the case of the FPGA pins the reasons are not quite so clear, but apparently sufficient impedance exists between the bidirectional cells and physical pins so that the input cell sees the value driven from the drive cell, not the value measured at the physical short. Again, the capture value is equal to the expected value, producing a PASS.

How can Mid-State Shorts be Detected?

As might be expected, MID-STATE shorts can be detected by a test pattern that uses tri-state, high impedance values, Z, in combination with zero and one values. One difficulty, however, is that since Z is a passive condition, this approach is likely to result in unpredictable numbers of false failures. Another problem is that the number of potential test scans required can be quite large.

onTAP addresses these difficulties in several ways. First, to achieve a manageable number of test patterns, standard Wagner test popular in boundary scan testing and known for their compactness and effectiveness, are employed. But instead of using only 0-1 test patterns, 0-Z and 1-Z patterns are also used. This is effective and will detect the shorts, but will inevitably also produce false failures.
To deal with the false failures, onTAP actively interrogates all indicted net combinations at run time with a more exhaustive
0-1-Z pattern that eliminates false failures but indicts any MID-STATE shorts
conditions.