Flynn Systems » boundary scan test

Properly Managing Common Tri-State Control Cells Boosts Fault Coverage

admin — Wed, 16 Dec 2009 20:16:00 +0000

As the boundary scan community continues looking for new ways to improve test procedures and achieve higher and higher fault coverage, we expect the test tools to compensate for shortcomings in silicon devices or board design. We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.

Common tri-state control cells are groups of pins on a common net. Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.

Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below.

In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.

The yellow 0 and 1 characters show drive, or boundary register update, values at each test vector, and the green L and H values show expected boundary register capture values on the vectors following an update.

This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.

This image shows how the test was revised to account for the tri-state pins on the common control cell. The result is a boost in fault coverage, with the added benefit of making the test more accurate.

As explained in the text box in this screen shot, onTAP accounts for the shared cells and adds additional test vectors to ensure pins do not drive simultaneously, allowing for more comprehensive tests that deliver higher, and most importantly, more accurate, test fault coverage.

Accepting New Turnkey JTAG Projects

admin — Tue, 17 Nov 2009 20:58:35 +0000

Flynn Systems wants to let our users know that we are accepting new JTAG / Boundary Scan projects for Q1-2/10

While our standard Technical Support provides assistance with test and development issues, our boundary scan test development services go beyond onTAP technical support services by taking the boundary scan / JTAG test development and debugging off your plate, allowing you to focus your undivided attention on your core business issues as you move through development and prototyping into manufacturing.

Our Boundary Scan Test Development Service is very popular with both existing and new customers. In fact, 4 out of 5 customers who have used onTAP boundary scan test development services once, immediately recognize the cost and time savings, and return within 4 months with another project. By turning over your JTAG / Boundary Scan test development to Flynn Systems, you are able focus on other aspects of your project without being distracted by developing and debugging boundary scan tests.

We ensure that your boundary scan tests are maximized for the highest possible fault coverage, are completely debugged, and are ready for the manufacturing floor, so the end user only has to “press a button.”

We support our tests and we will support you and/or your contract manufacturer by answering questions and bringing all parties involved up-to-speed with boundary scan test and onTAP procedures and reports.

Our test development features:

JTAG TAP infrastructure tests.
Interconnect tests including detection of opens, shorts, stuck-at, bus-wire, pull-up/down related faults.
Memory tests
Cluster tests of non-JTAG components
Flash programming
In-system programming configuration
Pin-level diagnostics
On-going support

All of our tests are comprehensive, accurate, supported and reliable.

Call us today to get started.

Click here to learn more about onTAP Turnkey Service

PC Based Parallel Test

admin — Fri, 30 Oct 2009 17:03:27 +0000

Ontap_parallel.exe can be used to simultaneously run test suites on multiple PC boards using the onTAP DLL. Parallel board testing must be enabled for the DLL license. Testing is fastest on a multiple processor PC , particularly where one core processor is available for each board. For example if four PC boards are being tested in parallel, then a quad core processor is recommended so that the time to test four boards is about the same as that required to test one board.

Procedure for Running Tests in Parallel

Create a separate folder for each board to be tested and in the folder place all of the tests that will be run for a board.

Launch an ontap_parallel.exe for each board to be tested, and for each instance of ontap_parallel.
exe, browse to a folder with the tests for a designated board. In the SVF Files list, check the SVF files that will be run for the board.

Return to the first instance of ontap_parallel.exe and check the boards that you wish to run in the Board list.

Click Run Checked Board Folders to run the tests for one or more folders. Test results are left in the .test and .fail files for each test in each folder. The test and diagnostic messages can be seen on the screen by selecting, as opposed to checking, a board and then selecting an SVF file.

Flynn Systems Announces upgraded Boundary Scan Tools: onTAP Series 4000

admin — Sat, 15 Nov 2008 15:52:48 +0000

Contact:

Wendy Harrison
Flynn Systems Corp.
74 Northeastern Blvd
STE 16A
Nashua, NH 03062-3192
USA
603-598-4444
Sales@flynn.com

Navigating the Scan Path to Higher Fault Coverage

NASHUA, NH August 15, 2008 – Flynn Systems Corp’s onTAP Series 4000 featuring their newest tool, ProScan, boosts fault coverage and increases visibility for Boundary Scan/JTAG 1149.1 testing through increased automation and graphical interfaces. By tapping its roots as a leader in Automatic Test Pattern Generation, Flynn Systems has seamlessly integrated ATPG for boundary scan circuits with ATPG algorithms for complex networks of non-scan circuits, such as logic elements, buffers, transceivers, and resistor networks that often lie between boundary scan pins.

“The goal is to exploit JTAG testing to achieve maximum fault coverage in addition to Flash programming and configuration tasks,” says Hank Flynn, CEO of Flynn Systems Corp. Like so many new features added to onTAP, Flynn’s introduction of the upgraded ATPG was a direct result of meeting customer needs. “Even if a tool has the capability to provide high fault coverage, when too much user intervention is required, chances are fault coverage goals will never be achieved. It’s clear that increased automation throughout the test prep experience is the key.” Says Flynn.

“When talking and meeting with customers, I recognized how easily fault coverage could be sacrificed in test preparation whenever the development software was not sufficiently helpful or too much user intervention was required. Development and test engineers are busy folks, so we had to make all aspects of boundary scan test development easy to use and understand and provide a software package that facilitates use of complex tools. This is where onTAP Series 4000 really opens doors.”

onTAP Series 4000 is a fully automated, netlist-based, boundary scan test, debug, and programming product. onTAP automatically initializes its ATPG algorithm to access a comprehensive library of models for non-scan devices, allowing it to manage and in effect to test through these devices. The user need only provide the BSDL files for the boundary scan/JTAG parts, and the netlist for the PCB. To make this process easier, Flynn Systems Corp. offers over 24 translators for popular CAD-based netlist formats, such as Allegro, EDIF, PADS, and OrCad. The test results are compiled into industry standard Serial Vector Format (SVF) files and supplementary diagnostic files used to provide pin-level diagnostic messages.

onTAP Series 4000 is part of a new series of testing and design tools from Flynn Systems offering greater flexibility, more automation and a more intuitive interface for novice boundary scan users and experts alike. Keep your eyes open for more advances in ease-of-use functionality from Flynn Systems this year.

About Flynn Systems:

Flynn Systems has provided test, debug, and programming solutions for the boundary scan test standard (JTAG IEEE 1149.1) for over ten years. Their onTAP software package is designed for completely automated boundary scan testing for devices of all levels of complexity on printed circuit boards (PCB) and non-boundary scan devices interacting with the scan enabled devices. onTAP’s functionality also includes the capability to program FLASH enabled devices using only the onTAP USB Test and Programming Cable. Flynn Systems Corp. provides high level test suites and the highest fault coverage available with a powerful ATG engine: all backed by fast, responsive technical support. Its satisfied customers include Intel, Qualcom, Harris RF, Benchmark Electronics, Raytheon, L-3 Communications, Cadence Design, Stanford Linear Accelerator, Teradyne, Checkpoint Systems, Ulticom, and University of Arizona. Flynn Systems’ onTAP provides boundary scan services for university research, avionics, defense systems, consumer goods, and medical electronics. It is based in New Hampshire with distributors and partners in Europe.

Those interested are invited to download a free 30 day evaluation software package with full technical support available at www.flynnsystems.com.