Properly Managing Common Tri-State Control Cells Boosts Fault Coverage

admin — Wed, 16 Dec 2009 20:16:00 +0000

As the boundary scan community continues looking for new ways to improve test procedures and achieve higher and higher fault coverage, we expect the test tools to compensate for shortcomings in silicon devices or board design. We are constantly exposed to new situations in boundary scan test and new approaches to using boundary scan to achieve better test fault coverage. One item standing in the way of higher, more accurate fault coverage is common tri-state control cells.

Common tri-state control cells are groups of pins on a common net. Just as the name suggests, they are tri-state pins, grouped together by a common function, sharing a boundary scan cell. Though this is efficient for circuitry, it poses some issues during JTAG test. For example, when a single pin on the common cell drives or senses a value, all the pins associated with that cell are forced to perform the same function, simultaneously. This is represented in the following drawing.

Un-handled common tri-state cells can have a negative impact on boundary scan test, dramatically reducing accuracy and fault coverage of opens and shorts tests because multiple pins sharing a common net drive in the same test vector, as displayed in the screen capture below.

In this image, you can see pins U23.AA14 and U36.AE30 are on net U23_AA14. This test is not accounting for the tri-state pins on the common control cell, ultimately compromising fault coverage.

The yellow 0 and 1 characters show drive, or boundary register update, values at each test vector, and the green L and H values show expected boundary register capture values on the vectors following an update.

This image shows the netlist view of the Mv6430 boundary scan device, while the following image displays the pins in an expanded view.

This image shows how the test was revised to account for the tri-state pins on the common control cell. The result is a boost in fault coverage, with the added benefit of making the test more accurate.

As explained in the text box in this screen shot, onTAP accounts for the shared cells and adds additional test vectors to ensure pins do not drive simultaneously, allowing for more comprehensive tests that deliver higher, and most importantly, more accurate, test fault coverage.

JTAG.TECT Reviews onTAP JTAG System

admin — Thu, 29 Oct 2009 20:10:21 +0000

Written by: Dr. Ami Gorodetsky of JTAG.TECT

Please follow this link for the original Russian:
http://www.jtag-test.ru/JTAGUniversity/articles/12-PE_6_2009.php

View Dr. Ami Gorodetsky’s blog:
http://moodle.cs.huji.ac.il/cs08/course/view.php?id=67703

In the 7^th paper of our “JTAG and DFT Basics Tutorial” series we had briefly examined the software basics of US based Flynn Systems’ (www.flynn.com ) onTAP Boundary Scan system that is intended for the JTAG test development, execution, and debugging, but the system hardware was not mentioned in the paper. In this sequential 12^th paper of the series we will overview the hardware of this very popular JTAG test system that is in worldwide usage for the JTAG-based test and in-circuit programming and flash burn-in stations, both in the lab environment and on the production facilities.

One of the noticeable and special features of the onTAP, which fairly distinguishes it from the hardware of competitor’s systems, is the surprising simplicity and mobility of the onTAP interface and, correspondingly, its low price. The onTAP hardware consists of the following three groups: two interface USB-adapters (the 6 MHz FS-9160 and the 30 MHz Dual Channel FS-9165), the FS-9180 TAP Serializer and GPIO Board, and a series of parallel JTAG-cables of different vendors (Xilinx, Altera, Lattice, etc.) that onTAP also supports. Designation of both USB-adapters, connected between a user’s PC and the UUT, is to support the operating voltages in the range of 1.8V to 5V, to increase the loading capacity and noise protection of the JTAG bus, and therefore, notably increasing the permissible distance between the PC-based test station and the UUT without any additional TCK frequency constraints.

The USB interface adapters together with the onTAP software allow for an easy and very mobile platform, without any noticeable limitations, to enlarge a quantity of JTAG chains utilized in the test, identical or different. In other words, the JTAG test preparation for a printed circuit board that contains n JTAG chains requires to have n FS-9160 adapters, or n/2 FS-9165adapters. With the usage of the FS-9180 TAP Serializer and GPIO Board the number of adapters can be substantially reduced. The same hardware setup (with the FS-9180 TAP Serializer or without it) also supports the simultaneous testing of n identical printed circuit boards with one or several JTAG chains; this situation is frequently encountered during the testing of similar printed circuit boards in mass production.

Flynn Systems » DFT and JTAG test

Properly Managing Common Tri-State Control Cells Boosts Fault Coverage

JTAG.TECT Reviews onTAP JTAG System